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pci/pci_expander_bridge: For CXL HB delay the HB register memory region setup.

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As the CXLState will no long be accessible via MachineState
at time of PXB_CXL realization, come back later from the machine specific
code to fill in the missing memory region setup. Only at this stage
is it possible to check if cxl=on, so that check is moved to this
later point.

Note that for multiple host bridges, the allocation order of the
register spaces is changed. This will be reflected in ACPI CEDT.

Stubs are added to handle case of CONFIG_PXB=n for machines that
call these functions.

The bus walking logic is common to all machines so add a utility
function + stub to cxl-host*.

Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Message-Id: <20220608145440.26106-6-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Jonathan Cameron 2022-06-08 15:54:37 +01:00 • committed by Michael S. Tsirkin
parent 96f7da1711
commit 7bd1900b36
8 changed files with 75 additions and 13 deletions
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12
include/hw/pci-bridge/pci_expander_bridge.h Normal file
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/*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#ifndef PCI_EXPANDER_BRIDGE_H
#define PCI_EXPANDER_BRIDGE_H
#include "hw/cxl/cxl.h"
void pxb_cxl_hook_up_registers(CXLState *state, PCIBus *bus, Error **errp);
#endif /* PCI_EXPANDER_BRIDGE_H */