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target/ppc/power8-pmu.c: add PM_RUN_INST_CMPL (0xFA) event

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PM_RUN_INST_CMPL, instructions completed with the run latch set, is
the architected PowerISA v3.1 event defined with PMC4SEL = 0xFA.

Implement it by checking for the CTRL RUN bit before incrementing the
counter. To make this work properly we also need to force a new
translation block each time SPR_CTRL is written. A small tweak in
pmu_increment_insns() is then needed to only increment this event
if the thread has the run latch.

Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211201151734.654994-8-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
This commit is contained in:
Daniel Henrique Barboza 2021-12-17 17:57:18 +01:00 • committed by Cédric Le Goater
parent 46d396bde9
commit 7aeac354a6
5 changed files with 42 additions and 4 deletions
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4
target/ppc/cpu.h
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@ -303,6 +303,7 @@ typedef enum {
PMU_EVENT_INACTIVE,
PMU_EVENT_CYCLES,
PMU_EVENT_INSTRUCTIONS,
PMU_EVENT_INSN_RUN_LATCH,
} PMUEventType;
/*****************************************************************************/
@ -388,6 +389,9 @@ typedef enum {
#define MMCR1_PMC4SEL_START 56
#define MMCR1_PMC4EVT_EXTR (64 - MMCR1_PMC4SEL_START - MMCR1_EVT_SIZE)
/* PMU uses CTRL_RUN to sample PM_RUN_INST_CMPL */
#define CTRL_RUN PPC_BIT(63)
/* LPCR bits */
#define LPCR_VPM0 PPC_BIT(0)
#define LPCR_VPM1 PPC_BIT(1)