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include/hw/riscv/opentitan: update opentitan IRQs

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Updates the opentitan IRQs to match the latest supported commit of
Opentitan from TockOS.

OPENTITAN_SUPPORTED_SHA := 565e4af39760a123c59a184aa2f5812a961fde47

Memory layout as per [1]

[1] 565e4af397/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h

Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230123063619.222459-1-wilfred.mallawa@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Wilfred Mallawa 2023-01-23 16:36:21 +10:00 • committed by Alistair Francis
parent 3de1fb712a
commit 7ae7146287
2 changed files with 47 additions and 47 deletions
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14
include/hw/riscv/opentitan.h
View file

@ -94,9 +94,9 @@ enum {
IBEX_DEV_EDNO,
IBEX_DEV_EDN1,
IBEX_DEV_ALERT_HANDLER,
IBEX_DEV_NMI_GEN,
IBEX_DEV_SRAM_CTRL,
IBEX_DEV_OTBN,
IBEX_DEV_PERI,
IBEX_DEV_IBEX_CFG,
};
enum {
@ -108,11 +108,11 @@ enum {
IBEX_UART0_RX_BREAK_ERR_IRQ = 6,
IBEX_UART0_RX_TIMEOUT_IRQ = 7,
IBEX_UART0_RX_PARITY_ERR_IRQ = 8,
IBEX_TIMER_TIMEREXPIRED0_0 = 127,
IBEX_SPI_HOST0_ERR_IRQ = 134,
IBEX_SPI_HOST0_SPI_EVENT_IRQ = 135,
IBEX_SPI_HOST1_ERR_IRQ = 136,
IBEX_SPI_HOST1_SPI_EVENT_IRQ = 137,
IBEX_TIMER_TIMEREXPIRED0_0 = 124,
IBEX_SPI_HOST0_ERR_IRQ = 131,
IBEX_SPI_HOST0_SPI_EVENT_IRQ = 132,
IBEX_SPI_HOST1_ERR_IRQ = 133,
IBEX_SPI_HOST1_SPI_EVENT_IRQ = 134,
};
#endif