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hw/timer: RX62N 8-Bit timer (TMR)

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renesas_tmr: 8bit timer modules.
This part use many renesas's CPU.
Hardware manual.
https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf

Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200224141923.82118-16-ysato@users.sourceforge.jp>
[PMD: Split from CMT, filled VMStateField for migration]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
This commit is contained in:
Yoshinori Sato 2019-03-20 23:16:05 +09:00 • committed by Philippe Mathieu-Daudé
parent e78597cc45
commit 7adca78eda
5 changed files with 538 additions and 0 deletions
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55
include/hw/timer/renesas_tmr.h Normal file
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/*
* Renesas 8bit timer Object
*
* Copyright (c) 2018 Yoshinori Sato
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#ifndef HW_TIMER_RENESAS_TMR_H
#define HW_TIMER_RENESAS_TMR_H
#include "qemu/timer.h"
#include "hw/sysbus.h"
#define TYPE_RENESAS_TMR "renesas-tmr"
#define RTMR(obj) OBJECT_CHECK(RTMRState, (obj), TYPE_RENESAS_TMR)
enum timer_event {
cmia = 0,
cmib = 1,
ovi = 2,
none = 3,
TMR_NR_EVENTS = 4
};
enum {
TMR_CH = 2,
TMR_NR_IRQ = 3 * TMR_CH
};
typedef struct RTMRState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
uint64_t input_freq;
MemoryRegion memory;
int64_t tick;
uint8_t tcnt[TMR_CH];
uint8_t tcora[TMR_CH];
uint8_t tcorb[TMR_CH];
uint8_t tcr[TMR_CH];
uint8_t tccr[TMR_CH];
uint8_t tcor[TMR_CH];
uint8_t tcsr[TMR_CH];
int64_t div_round[TMR_CH];
uint8_t next[TMR_CH];
qemu_irq cmia[TMR_CH];
qemu_irq cmib[TMR_CH];
qemu_irq ovi[TMR_CH];
QEMUTimer timer[TMR_CH];
} RTMRState;
#endif