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target/riscv: Add *envcfg.PBMTE related check in address translation

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menvcfg.PBMTE bit controls whether the Svpbmt extension is available
for use in S-mode and G-stage address translation.

henvcfg.PBMTE bit controls whether the Svpbmt extension is available
for use in VS-stage address translation.

Set *envcfg.PBMTE default true for backward compatibility.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230224040852.37109-5-liweiwei@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
This commit is contained in:
Weiwei Li 2023-02-24 12:08:50 +08:00 • committed by Palmer Dabbelt
parent 0d190bd394
commit 7a6613da99
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GPG key ID: 2E1319F35FBB1889
2 changed files with 11 additions and 2 deletions
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10
target/riscv/cpu_helper.c
View file

@ -936,9 +936,15 @@ restart:
return TRANSLATE_FAIL;
}
bool pbmte = env->menvcfg & MENVCFG_PBMTE;
if (first_stage && two_stage && riscv_cpu_virt_enabled(env)) {
pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE);
}
if (riscv_cpu_sxl(env) == MXL_RV32) {
ppn = pte >> PTE_PPN_SHIFT;
} else if (cpu->cfg.ext_svpbmt || cpu->cfg.ext_svnapot) {
} else if (pbmte || cpu->cfg.ext_svnapot) {
ppn = (pte & (target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT;
} else {
ppn = pte >> PTE_PPN_SHIFT;
@ -950,7 +956,7 @@ restart:
if (!(pte & PTE_V)) {
/* Invalid PTE */
return TRANSLATE_FAIL;
} else if (!cpu->cfg.ext_svpbmt && (pte & PTE_PBMT)) {
} else if (!pbmte && (pte & PTE_PBMT)) {
return TRANSLATE_FAIL;
} else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
/* Inner PTE, continue walking */