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ppc patch queue 2021-01-06

Browse source 
First pull request for 2021, which has a bunch of things accumulated
 over the holidays.  Includes:
   * A number of cleanups to sam460ex and ppc440 code from BALATON Zoltan
   * Several fixes for builds with --without-default-devices from Greg Kurz
   * Fixes for some DRC reset problems from Greg Kurz
   * QOM conversion of the PPC 4xx UIC devices from Peter Maydell
   * Some other assorted fixes and cleanups
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Merge remote-tracking branch 'remotes/dg-gitlab/tags/ppc-for-6.0-20210106' into staging

ppc patch queue 2021-01-06

First pull request for 2021, which has a bunch of things accumulated
over the holidays.  Includes:
  * A number of cleanups to sam460ex and ppc440 code from BALATON Zoltan
  * Several fixes for builds with --without-default-devices from Greg Kurz
  * Fixes for some DRC reset problems from Greg Kurz
  * QOM conversion of the PPC 4xx UIC devices from Peter Maydell
  * Some other assorted fixes and cleanups

# gpg: Signature made Wed 06 Jan 2021 03:33:19 GMT
# gpg:                using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392
# gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" [full]
# gpg:                 aka "David Gibson (Red Hat) <dgibson@redhat.com>" [full]
# gpg:                 aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" [full]
# gpg:                 aka "David Gibson (kernel.org) <dwg@kernel.org>" [unknown]
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E  87DC 6C38 CACA 20D9 B392

* remotes/dg-gitlab/tags/ppc-for-6.0-20210106: (22 commits)
  ppc440_pcix: Fix up pci config access
  ppc440_pcix: Fix register write trace event
  ppc440_pcix: Improve comment for IRQ mapping
  sam460ex: Remove FDT_PPC dependency from KConfig
  ppc4xx: Move common dependency on serial to common option
  pnv: Fix reverse dependency on PCI express root ports
  ppc: Simplify reverse dependencies of POWERNV and PSERIES on XICS and XIVE
  ppc: Fix build with --without-default-devices
  spapr: Add drc_ prefix to the DRC realize and unrealize functions
  spapr: Use spapr_drc_reset_all() at machine reset
  spapr: Introduce spapr_drc_reset_all()
  spapr: Fix reset of transient DR connectors
  spapr: Call spapr_drc_reset() for all DRCs at CAS
  spapr: Fix buffer overflow in spapr_numa_associativity_init()
  spapr: Allow memory unplug to always succeed
  spapr: Fix DR properties of the root node
  spapr/xive: Make spapr_xive_pic_print_info() static
  spapr: DRC lookup cannot fail
  hw/ppc/ppc440_bamboo: Drop use of ppcuic_init()
  hw/ppc/virtex_ml507: Drop use of ppcuic_init()
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2021-01-06 11:24:11 +00:00
commit 7a5fd9343d
22 changed files with 616 additions and 383 deletions
Download patch file Download diff file Expand all files Collapse all files

73
include/hw/intc/ppc-uic.h Normal file
View file

@ -0,0 +1,73 @@
/*
* "Universal" Interrupt Controller for PowerPPC 4xx embedded processors
*
* Copyright (c) 2007 Jocelyn Mayer
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef HW_INTC_PPC_UIC_H
#define HW_INTC_PPC_UIC_H
#include "hw/sysbus.h"
#include "qom/object.h"
#define TYPE_PPC_UIC "ppc-uic"
OBJECT_DECLARE_SIMPLE_TYPE(PPCUIC, PPC_UIC)
/*
* QEMU interface:
* QOM property "cpu": link to the PPC CPU
* (no default, must be set)
* QOM property "dcr-base": base of the bank of DCR registers for the UIC
* (default 0x30)
* QOM property "use-vectors": true if the UIC has vector registers
* (default true)
* unnamed GPIO inputs 0..UIC_MAX_IRQ: input IRQ lines
* sysbus IRQs:
* 0 (PPCUIC_OUTPUT_INT): output INT line to the CPU
* 1 (PPCUIC_OUTPUT_CINT): output CINT line to the CPU
*/
#define UIC_MAX_IRQ 32
struct PPCUIC {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
qemu_irq output_int;
qemu_irq output_cint;
/* properties */
CPUState *cpu;
uint32_t dcr_base;
bool use_vectors;
uint32_t level; /* Remembers the state of level-triggered interrupts. */
uint32_t uicsr; /* Status register */
uint32_t uicer; /* Enable register */
uint32_t uiccr; /* Critical register */
uint32_t uicpr; /* Polarity register */
uint32_t uictr; /* Triggering register */
uint32_t uicvcr; /* Vector configuration register */
uint32_t uicvr;
};
#endif

2
include/hw/pci-host/spapr.h
View file

@ -115,8 +115,6 @@ struct SpaprPhbState {
#define SPAPR_PCI_NV2RAM64_WIN_BASE SPAPR_PCI_LIMIT
#define SPAPR_PCI_NV2RAM64_WIN_SIZE (2 * TiB) /* For up to 6 GPUs 256GB each */
/* Max number of these GPUsper a physical box */
#define NVGPU_MAX_NUM 6
/* Max number of NVLinks per GPU in any physical box */
#define NVGPU_MAX_LINKS 3

6
include/hw/ppc/spapr.h
View file

@ -112,6 +112,9 @@ typedef enum {
#define NUMA_ASSOC_SIZE (MAX_DISTANCE_REF_POINTS + 1)
#define VCPU_ASSOC_SIZE (NUMA_ASSOC_SIZE + 1)
/* Max number of these GPUsper a physical box */
#define NVGPU_MAX_NUM 6
typedef struct SpaprCapabilities SpaprCapabilities;
struct SpaprCapabilities {
uint8_t caps[SPAPR_CAP_NUM];
@ -139,6 +142,7 @@ struct SpaprMachineClass {
hwaddr rma_limit; /* clamp the RMA to this size */
bool pre_5_1_assoc_refpoints;
bool pre_5_2_numa_associativity;
bool pre_6_0_memory_unplug;
bool (*phb_placement)(SpaprMachineState *spapr, uint32_t index,
uint64_t *buid, hwaddr *pio,
@ -239,7 +243,7 @@ struct SpaprMachineState {
unsigned gpu_numa_id;
SpaprTpmProxy *tpm_proxy;
uint32_t numa_assoc_array[MAX_NODES][NUMA_ASSOC_SIZE];
uint32_t numa_assoc_array[MAX_NODES + NVGPU_MAX_NUM][NUMA_ASSOC_SIZE];
Error *fwnmi_migration_blocker;
};

10
include/hw/ppc/spapr_drc.h
View file

@ -224,7 +224,8 @@ static inline bool spapr_drc_hotplugged(DeviceState *dev)
return dev->hotplugged && !runstate_check(RUN_STATE_INMIGRATE);
}
void spapr_drc_reset(SpaprDrc *drc);
/* Returns true if an unplug request completed */
bool spapr_drc_reset(SpaprDrc *drc);
uint32_t spapr_drc_index(SpaprDrc *drc);
SpaprDrcType spapr_drc_type(SpaprDrc *drc);
@ -244,8 +245,11 @@ int spapr_dt_drc(void *fdt, int offset, Object *owner, uint32_t drc_type_mask);
void spapr_drc_attach(SpaprDrc *drc, DeviceState *d);
void spapr_drc_detach(SpaprDrc *drc);
/* Returns true if a hot plug/unplug request is pending */
bool spapr_drc_transient(SpaprDrc *drc);
/*
* Reset all DRCs, causing pending hot-plug/unplug requests to complete.
* Safely handles potential DRC removal (eg. PHBs or PCI bridges).
*/
void spapr_drc_reset_all(struct SpaprMachineState *spapr);
static inline bool spapr_drc_unplug_requested(SpaprDrc *drc)
{

2
include/hw/ppc/spapr_xive.h
View file

@ -66,8 +66,6 @@ typedef struct SpaprXiveClass {
*/
#define SPAPR_XIVE_BLOCK_ID 0x0
void spapr_xive_pic_print_info(SpaprXive *xive, Monitor *mon);
struct SpaprMachineState;
void spapr_xive_hcall_init(struct SpaprMachineState *spapr);
void spapr_xive_mmio_set_enabled(SpaprXive *xive, bool enable);