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https://github.com/Motorhead1991/qemu.git
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linux-headers: update
This updates linux-headers against master 4.1-rc1 (commit b787f68c36d49bb1d9236f403813641efa74a031). Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
This commit is contained in:
Cornelia Huck
parent
217a4acb21
commit
7a52ce8a16
10 changed files with 291 additions and 66 deletions
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@ -195,9 +195,16 @@ struct kvm_arch_memory_slot {
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#define KVM_ARM_IRQ_CPU_IRQ 0
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#define KVM_ARM_IRQ_CPU_FIQ 1
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/* Highest supported SPI, from VGIC_NR_IRQS */
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/*
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* This used to hold the highest supported SPI, but it is now obsolete
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* and only here to provide source code level compatibility with older
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* userland. The highest SPI number can be set via KVM_DEV_ARM_VGIC_GRP_NR_IRQS.
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*/
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#define KVM_ARM_IRQ_GIC_MAX 127
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/* One single KVM irqchip, ie. the VGIC */
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#define KVM_NR_IRQCHIPS 1
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/* PSCI interface */
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#define KVM_PSCI_FN_BASE 0x95c1ba5e
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#define KVM_PSCI_FN(n) (KVM_PSCI_FN_BASE + (n))
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@ -188,9 +188,16 @@ struct kvm_arch_memory_slot {
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#define KVM_ARM_IRQ_CPU_IRQ 0
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#define KVM_ARM_IRQ_CPU_FIQ 1
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/* Highest supported SPI, from VGIC_NR_IRQS */
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/*
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* This used to hold the highest supported SPI, but it is now obsolete
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* and only here to provide source code level compatibility with older
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* userland. The highest SPI number can be set via KVM_DEV_ARM_VGIC_GRP_NR_IRQS.
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*/
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#define KVM_ARM_IRQ_GIC_MAX 127
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/* One single KVM irqchip, ie. the VGIC */
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#define KVM_NR_IRQCHIPS 1
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/* PSCI interface */
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#define KVM_PSCI_FN_BASE 0x95c1ba5e
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#define KVM_PSCI_FN(n) (KVM_PSCI_FN_BASE + (n))
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@ -36,77 +36,85 @@ struct kvm_regs {
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/*
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* for KVM_GET_FPU and KVM_SET_FPU
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*
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* If Status[FR] is zero (32-bit FPU), the upper 32-bits of the FPRs
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* are zero filled.
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*/
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struct kvm_fpu {
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__u64 fpr[32];
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__u32 fir;
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__u32 fccr;
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__u32 fexr;
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__u32 fenr;
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__u32 fcsr;
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__u32 pad;
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};
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/*
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* For MIPS, we use KVM_SET_ONE_REG and KVM_GET_ONE_REG to access CP0
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* For MIPS, we use KVM_SET_ONE_REG and KVM_GET_ONE_REG to access various
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* registers. The id field is broken down as follows:
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*
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* bits[2..0] - Register 'sel' index.
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* bits[7..3] - Register 'rd' index.
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* bits[15..8] - Must be zero.
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* bits[31..16] - 1 -> CP0 registers.
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* bits[51..32] - Must be zero.
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* bits[63..52] - As per linux/kvm.h
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* bits[51..32] - Must be zero.
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* bits[31..16] - Register set.
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*
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* Register set = 0: GP registers from kvm_regs (see definitions below).
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*
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* Register set = 1: CP0 registers.
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* bits[15..8] - Must be zero.
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* bits[7..3] - Register 'rd' index.
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* bits[2..0] - Register 'sel' index.
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*
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* Register set = 2: KVM specific registers (see definitions below).
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*
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* Register set = 3: FPU / MSA registers (see definitions below).
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*
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* Other sets registers may be added in the future. Each set would
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* have its own identifier in bits[31..16].
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*
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* The registers defined in struct kvm_regs are also accessible, the
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* id values for these are below.
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*/
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#define KVM_REG_MIPS_R0 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 0)
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#define KVM_REG_MIPS_R1 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 1)
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#define KVM_REG_MIPS_R2 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 2)
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#define KVM_REG_MIPS_R3 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 3)
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#define KVM_REG_MIPS_R4 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 4)
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#define KVM_REG_MIPS_R5 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 5)
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#define KVM_REG_MIPS_R6 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 6)
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#define KVM_REG_MIPS_R7 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 7)
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#define KVM_REG_MIPS_R8 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 8)
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#define KVM_REG_MIPS_R9 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 9)
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#define KVM_REG_MIPS_R10 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 10)
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#define KVM_REG_MIPS_R11 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 11)
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#define KVM_REG_MIPS_R12 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 12)
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#define KVM_REG_MIPS_R13 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 13)
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#define KVM_REG_MIPS_R14 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 14)
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#define KVM_REG_MIPS_R15 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 15)
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#define KVM_REG_MIPS_R16 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 16)
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#define KVM_REG_MIPS_R17 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 17)
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#define KVM_REG_MIPS_R18 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 18)
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#define KVM_REG_MIPS_R19 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 19)
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#define KVM_REG_MIPS_R20 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 20)
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#define KVM_REG_MIPS_R21 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 21)
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#define KVM_REG_MIPS_R22 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 22)
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#define KVM_REG_MIPS_R23 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 23)
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#define KVM_REG_MIPS_R24 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 24)
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#define KVM_REG_MIPS_R25 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 25)
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#define KVM_REG_MIPS_R26 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 26)
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#define KVM_REG_MIPS_R27 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 27)
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#define KVM_REG_MIPS_R28 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 28)
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#define KVM_REG_MIPS_R29 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 29)
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#define KVM_REG_MIPS_R30 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 30)
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#define KVM_REG_MIPS_R31 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 31)
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#define KVM_REG_MIPS_GP (KVM_REG_MIPS | 0x0000000000000000ULL)
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#define KVM_REG_MIPS_CP0 (KVM_REG_MIPS | 0x0000000000010000ULL)
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#define KVM_REG_MIPS_KVM (KVM_REG_MIPS | 0x0000000000020000ULL)
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#define KVM_REG_MIPS_FPU (KVM_REG_MIPS | 0x0000000000030000ULL)
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#define KVM_REG_MIPS_HI (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 32)
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#define KVM_REG_MIPS_LO (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 33)
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#define KVM_REG_MIPS_PC (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 34)
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/* KVM specific control registers */
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/*
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* KVM_REG_MIPS_GP - General purpose registers from kvm_regs.
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*/
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#define KVM_REG_MIPS_R0 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 0)
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#define KVM_REG_MIPS_R1 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 1)
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#define KVM_REG_MIPS_R2 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 2)
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#define KVM_REG_MIPS_R3 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 3)
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#define KVM_REG_MIPS_R4 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 4)
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#define KVM_REG_MIPS_R5 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 5)
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#define KVM_REG_MIPS_R6 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 6)
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#define KVM_REG_MIPS_R7 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 7)
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#define KVM_REG_MIPS_R8 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 8)
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#define KVM_REG_MIPS_R9 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 9)
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#define KVM_REG_MIPS_R10 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 10)
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#define KVM_REG_MIPS_R11 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 11)
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#define KVM_REG_MIPS_R12 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 12)
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#define KVM_REG_MIPS_R13 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 13)
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#define KVM_REG_MIPS_R14 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 14)
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#define KVM_REG_MIPS_R15 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 15)
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#define KVM_REG_MIPS_R16 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 16)
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#define KVM_REG_MIPS_R17 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 17)
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#define KVM_REG_MIPS_R18 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 18)
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#define KVM_REG_MIPS_R19 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 19)
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#define KVM_REG_MIPS_R20 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 20)
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#define KVM_REG_MIPS_R21 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 21)
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#define KVM_REG_MIPS_R22 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 22)
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#define KVM_REG_MIPS_R23 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 23)
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#define KVM_REG_MIPS_R24 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 24)
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#define KVM_REG_MIPS_R25 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 25)
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#define KVM_REG_MIPS_R26 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 26)
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#define KVM_REG_MIPS_R27 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 27)
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#define KVM_REG_MIPS_R28 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 28)
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#define KVM_REG_MIPS_R29 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 29)
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#define KVM_REG_MIPS_R30 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 30)
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#define KVM_REG_MIPS_R31 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 31)
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#define KVM_REG_MIPS_HI (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 32)
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#define KVM_REG_MIPS_LO (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 33)
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#define KVM_REG_MIPS_PC (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 34)
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/*
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* KVM_REG_MIPS_KVM - KVM specific control registers.
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*/
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/*
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* CP0_Count control
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@ -118,8 +126,7 @@ struct kvm_fpu {
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* safely without losing time or guest timer interrupts.
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* Other: Reserved, do not change.
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*/
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#define KVM_REG_MIPS_COUNT_CTL (KVM_REG_MIPS | KVM_REG_SIZE_U64 | \
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0x20000 | 0)
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#define KVM_REG_MIPS_COUNT_CTL (KVM_REG_MIPS_KVM | KVM_REG_SIZE_U64 | 0)
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#define KVM_REG_MIPS_COUNT_CTL_DC 0x00000001
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/*
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@ -131,15 +138,46 @@ struct kvm_fpu {
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* emulated.
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* Modifications to times in the future are rejected.
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*/
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#define KVM_REG_MIPS_COUNT_RESUME (KVM_REG_MIPS | KVM_REG_SIZE_U64 | \
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0x20000 | 1)
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#define KVM_REG_MIPS_COUNT_RESUME (KVM_REG_MIPS_KVM | KVM_REG_SIZE_U64 | 1)
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/*
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* CP0_Count rate in Hz
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* Specifies the rate of the CP0_Count timer in Hz. Modifications occur without
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* discontinuities in CP0_Count.
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*/
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#define KVM_REG_MIPS_COUNT_HZ (KVM_REG_MIPS | KVM_REG_SIZE_U64 | \
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0x20000 | 2)
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#define KVM_REG_MIPS_COUNT_HZ (KVM_REG_MIPS_KVM | KVM_REG_SIZE_U64 | 2)
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/*
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* KVM_REG_MIPS_FPU - Floating Point and MIPS SIMD Architecture (MSA) registers.
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*
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* bits[15..8] - Register subset (see definitions below).
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* bits[7..5] - Must be zero.
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* bits[4..0] - Register number within register subset.
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*/
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#define KVM_REG_MIPS_FPR (KVM_REG_MIPS_FPU | 0x0000000000000000ULL)
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#define KVM_REG_MIPS_FCR (KVM_REG_MIPS_FPU | 0x0000000000000100ULL)
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#define KVM_REG_MIPS_MSACR (KVM_REG_MIPS_FPU | 0x0000000000000200ULL)
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/*
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* KVM_REG_MIPS_FPR - Floating point / Vector registers.
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*/
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#define KVM_REG_MIPS_FPR_32(n) (KVM_REG_MIPS_FPR | KVM_REG_SIZE_U32 | (n))
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#define KVM_REG_MIPS_FPR_64(n) (KVM_REG_MIPS_FPR | KVM_REG_SIZE_U64 | (n))
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#define KVM_REG_MIPS_VEC_128(n) (KVM_REG_MIPS_FPR | KVM_REG_SIZE_U128 | (n))
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/*
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* KVM_REG_MIPS_FCR - Floating point control registers.
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*/
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#define KVM_REG_MIPS_FCR_IR (KVM_REG_MIPS_FCR | KVM_REG_SIZE_U32 | 0)
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#define KVM_REG_MIPS_FCR_CSR (KVM_REG_MIPS_FCR | KVM_REG_SIZE_U32 | 31)
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/*
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* KVM_REG_MIPS_MSACR - MIPS SIMD Architecture (MSA) control registers.
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*/
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#define KVM_REG_MIPS_MSA_IR (KVM_REG_MIPS_MSACR | KVM_REG_SIZE_U32 | 0)
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#define KVM_REG_MIPS_MSA_CSR (KVM_REG_MIPS_MSACR | KVM_REG_SIZE_U32 | 1)
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/*
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* KVM MIPS specific structures and definitions
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@ -150,6 +150,7 @@ struct kvm_guest_debug_arch {
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#define KVM_SYNC_CRS (1UL << 3)
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#define KVM_SYNC_ARCH0 (1UL << 4)
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#define KVM_SYNC_PFAULT (1UL << 5)
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#define KVM_SYNC_VRS (1UL << 6)
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/* definition of registers in kvm_run */
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struct kvm_sync_regs {
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__u64 prefix; /* prefix register */
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@ -164,6 +165,9 @@ struct kvm_sync_regs {
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__u64 pft; /* pfault token [PFAULT] */
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__u64 pfs; /* pfault select [PFAULT] */
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__u64 pfc; /* pfault compare [PFAULT] */
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__u64 vrs[32][2]; /* vector registers */
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__u8 reserved[512]; /* for future vector expansion */
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__u32 fpc; /* only valid with vector registers */
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};
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#define KVM_REG_S390_TODPR (KVM_REG_S390 | KVM_REG_SIZE_U32 | 0x1)
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@ -225,6 +225,8 @@
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#define HV_STATUS_INVALID_HYPERCALL_CODE 2
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#define HV_STATUS_INVALID_HYPERCALL_INPUT 3
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#define HV_STATUS_INVALID_ALIGNMENT 4
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#define HV_STATUS_INSUFFICIENT_MEMORY 11
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#define HV_STATUS_INVALID_CONNECTION_ID 18
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#define HV_STATUS_INSUFFICIENT_BUFFERS 19
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typedef struct _HV_REFERENCE_TSC_PAGE {
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@ -147,6 +147,16 @@ struct kvm_pit_config {
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#define KVM_PIT_SPEAKER_DUMMY 1
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struct kvm_s390_skeys {
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__u64 start_gfn;
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__u64 count;
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__u64 skeydata_addr;
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__u32 flags;
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__u32 reserved[9];
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};
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#define KVM_S390_GET_SKEYS_NONE 1
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#define KVM_S390_SKEYS_MAX 1048576
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#define KVM_EXIT_UNKNOWN 0
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#define KVM_EXIT_EXCEPTION 1
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#define KVM_EXIT_IO 2
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@ -172,6 +182,7 @@ struct kvm_pit_config {
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#define KVM_EXIT_S390_TSCH 22
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#define KVM_EXIT_EPR 23
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#define KVM_EXIT_SYSTEM_EVENT 24
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#define KVM_EXIT_S390_STSI 25
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/* For KVM_EXIT_INTERNAL_ERROR */
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/* Emulate instruction failed. */
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@ -309,6 +320,15 @@ struct kvm_run {
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__u32 type;
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__u64 flags;
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} system_event;
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/* KVM_EXIT_S390_STSI */
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struct {
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__u64 addr;
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__u8 ar;
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__u8 reserved;
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__u8 fc;
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__u8 sel1;
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__u16 sel2;
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} s390_stsi;
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/* Fix the size of the union. */
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char padding[256];
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};
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@ -324,7 +344,7 @@ struct kvm_run {
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__u64 kvm_dirty_regs;
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union {
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struct kvm_sync_regs regs;
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char padding[1024];
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char padding[2048];
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} s;
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};
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@ -365,6 +385,24 @@ struct kvm_translation {
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__u8 pad[5];
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};
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/* for KVM_S390_MEM_OP */
|
||||
struct kvm_s390_mem_op {
|
||||
/* in */
|
||||
__u64 gaddr; /* the guest address */
|
||||
__u64 flags; /* flags */
|
||||
__u32 size; /* amount of bytes */
|
||||
__u32 op; /* type of operation */
|
||||
__u64 buf; /* buffer in userspace */
|
||||
__u8 ar; /* the access register number */
|
||||
__u8 reserved[31]; /* should be set to 0 */
|
||||
};
|
||||
/* types for kvm_s390_mem_op->op */
|
||||
#define KVM_S390_MEMOP_LOGICAL_READ 0
|
||||
#define KVM_S390_MEMOP_LOGICAL_WRITE 1
|
||||
/* flags for kvm_s390_mem_op->flags */
|
||||
#define KVM_S390_MEMOP_F_CHECK_ONLY (1ULL << 0)
|
||||
#define KVM_S390_MEMOP_F_INJECT_EXCEPTION (1ULL << 1)
|
||||
|
||||
/* for KVM_INTERRUPT */
|
||||
struct kvm_interrupt {
|
||||
/* in */
|
||||
|
|
@ -520,6 +558,13 @@ struct kvm_s390_irq {
|
|||
} u;
|
||||
};
|
||||
|
||||
struct kvm_s390_irq_state {
|
||||
__u64 buf;
|
||||
__u32 flags;
|
||||
__u32 len;
|
||||
__u32 reserved[4];
|
||||
};
|
||||
|
||||
/* for KVM_SET_GUEST_DEBUG */
|
||||
|
||||
#define KVM_GUESTDBG_ENABLE 0x00000001
|
||||
|
|
@ -760,6 +805,15 @@ struct kvm_ppc_smmu_info {
|
|||
#define KVM_CAP_PPC_ENABLE_HCALL 104
|
||||
#define KVM_CAP_CHECK_EXTENSION_VM 105
|
||||
#define KVM_CAP_S390_USER_SIGP 106
|
||||
#define KVM_CAP_S390_VECTOR_REGISTERS 107
|
||||
#define KVM_CAP_S390_MEM_OP 108
|
||||
#define KVM_CAP_S390_USER_STSI 109
|
||||
#define KVM_CAP_S390_SKEYS 110
|
||||
#define KVM_CAP_MIPS_FPU 111
|
||||
#define KVM_CAP_MIPS_MSA 112
|
||||
#define KVM_CAP_S390_INJECT_IRQ 113
|
||||
#define KVM_CAP_S390_IRQ_STATE 114
|
||||
#define KVM_CAP_PPC_HWRNG 115
|
||||
|
||||
#ifdef KVM_CAP_IRQ_ROUTING
|
||||
|
||||
|
|
@ -1135,6 +1189,16 @@ struct kvm_s390_ucas_mapping {
|
|||
#define KVM_ARM_VCPU_INIT _IOW(KVMIO, 0xae, struct kvm_vcpu_init)
|
||||
#define KVM_ARM_PREFERRED_TARGET _IOR(KVMIO, 0xaf, struct kvm_vcpu_init)
|
||||
#define KVM_GET_REG_LIST _IOWR(KVMIO, 0xb0, struct kvm_reg_list)
|
||||
/* Available with KVM_CAP_S390_MEM_OP */
|
||||
#define KVM_S390_MEM_OP _IOW(KVMIO, 0xb1, struct kvm_s390_mem_op)
|
||||
/* Available with KVM_CAP_S390_SKEYS */
|
||||
#define KVM_S390_GET_SKEYS _IOW(KVMIO, 0xb2, struct kvm_s390_skeys)
|
||||
#define KVM_S390_SET_SKEYS _IOW(KVMIO, 0xb3, struct kvm_s390_skeys)
|
||||
/* Available with KVM_CAP_S390_INJECT_IRQ */
|
||||
#define KVM_S390_IRQ _IOW(KVMIO, 0xb4, struct kvm_s390_irq)
|
||||
/* Available with KVM_CAP_S390_IRQ_STATE */
|
||||
#define KVM_S390_SET_IRQ_STATE _IOW(KVMIO, 0xb5, struct kvm_s390_irq_state)
|
||||
#define KVM_S390_GET_IRQ_STATE _IOW(KVMIO, 0xb6, struct kvm_s390_irq_state)
|
||||
|
||||
#define KVM_DEV_ASSIGN_ENABLE_IOMMU (1 << 0)
|
||||
#define KVM_DEV_ASSIGN_PCI_2_3 (1 << 1)
|
||||
|
|
|
|||
|
|
@ -160,6 +160,8 @@ struct vfio_device_info {
|
|||
__u32 flags;
|
||||
#define VFIO_DEVICE_FLAGS_RESET (1 << 0) /* Device supports reset */
|
||||
#define VFIO_DEVICE_FLAGS_PCI (1 << 1) /* vfio-pci device */
|
||||
#define VFIO_DEVICE_FLAGS_PLATFORM (1 << 2) /* vfio-platform device */
|
||||
#define VFIO_DEVICE_FLAGS_AMBA (1 << 3) /* vfio-amba device */
|
||||
__u32 num_regions; /* Max region index + 1 */
|
||||
__u32 num_irqs; /* Max IRQ index + 1 */
|
||||
};
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue