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target/riscv: Move gen_arith_imm() decoding into trans_* functions

Browse source 
gen_arith_imm() does a lot of decoding manually, which was hard to read
in case of the shift instructions and is not necessary anymore with
decodetree.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
This commit is contained in:
Bastian Koppelmann 2019-02-13 07:54:03 -08:00
parent bce8a342a1
commit 7a50d3e2ae
3 changed files with 108 additions and 100 deletions
Download patch file Download diff file Expand all files Collapse all files

107
target/riscv/translate.c
View file

@ -433,86 +433,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1,
tcg_temp_free(source2);
}
static void gen_arith_imm(DisasContext *ctx, uint32_t opc, int rd,
int rs1, target_long imm)
{
TCGv source1 = tcg_temp_new();
int shift_len = TARGET_LONG_BITS;
int shift_a;
gen_get_gpr(source1, rs1);
switch (opc) {
case OPC_RISC_ADDI:
#if defined(TARGET_RISCV64)
case OPC_RISC_ADDIW:
#endif
tcg_gen_addi_tl(source1, source1, imm);
break;
case OPC_RISC_SLTI:
tcg_gen_setcondi_tl(TCG_COND_LT, source1, source1, imm);
break;
case OPC_RISC_SLTIU:
tcg_gen_setcondi_tl(TCG_COND_LTU, source1, source1, imm);
break;
case OPC_RISC_XORI:
tcg_gen_xori_tl(source1, source1, imm);
break;
case OPC_RISC_ORI:
tcg_gen_ori_tl(source1, source1, imm);
break;
case OPC_RISC_ANDI:
tcg_gen_andi_tl(source1, source1, imm);
break;
#if defined(TARGET_RISCV64)
case OPC_RISC_SLLIW:
shift_len = 32;
/* FALLTHRU */
#endif
case OPC_RISC_SLLI:
if (imm >= shift_len) {
goto do_illegal;
}
tcg_gen_shli_tl(source1, source1, imm);
break;
#if defined(TARGET_RISCV64)
case OPC_RISC_SHIFT_RIGHT_IW:
shift_len = 32;
/* FALLTHRU */
#endif
case OPC_RISC_SHIFT_RIGHT_I:
/* differentiate on IMM */
shift_a = imm & 0x400;
imm &= 0x3ff;
if (imm >= shift_len) {
goto do_illegal;
}
if (imm != 0) {
if (shift_a) {
/* SRAI[W] */
tcg_gen_sextract_tl(source1, source1, imm, shift_len - imm);
} else {
/* SRLI[W] */
tcg_gen_extract_tl(source1, source1, imm, shift_len - imm);
}
/* No further sign-extension needed for W instructions. */
opc &= ~0x8;
}
break;
default:
do_illegal:
gen_exception_illegal(ctx);
return;
}
if (opc & 0x8) { /* sign-extend for W instructions */
tcg_gen_ext32s_tl(source1, source1);
}
gen_set_gpr(rd, source1);
tcg_temp_free(source1);
}
static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
{
target_ulong next_pc;
@ -785,6 +705,33 @@ static int ex_rvc_register(int reg)
bool decode_insn32(DisasContext *ctx, uint32_t insn);
/* Include the auto-generated decoder for 32 bit insn */
#include "decode_insn32.inc.c"
static bool gen_arith_imm(DisasContext *ctx, arg_i *a,
void(*func)(TCGv, TCGv, TCGv))
{
TCGv source1, source2;
source1 = tcg_temp_new();
source2 = tcg_temp_new();
gen_get_gpr(source1, a->rs1);
tcg_gen_movi_tl(source2, a->imm);
(*func)(source1, source1, source2);
gen_set_gpr(a->rd, source1);
tcg_temp_free(source1);
tcg_temp_free(source2);
return true;
}
#ifdef TARGET_RISCV64
static void gen_addw(TCGv ret, TCGv arg1, TCGv arg2)
{
tcg_gen_add_tl(ret, arg1, arg2);
tcg_gen_ext32s_tl(ret, ret);
}
#endif
/* Include insn module translation function */
#include "insn_trans/trans_rvi.inc.c"
#include "insn_trans/trans_rvm.inc.c"