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target/riscv: Adjust pmpcfg access with mxl

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Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-2-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
LIU Zhiwei 2022-01-20 20:20:28 +08:00 • committed by Alistair Francis
parent 4211fc5532
commit 79f26b3b95
2 changed files with 23 additions and 8 deletions
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19
target/riscv/csr.c
View file

@ -1497,9 +1497,23 @@ static RISCVException write_mseccfg(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE; return RISCV_EXCP_NONE;
} }
static bool check_pmp_reg_index(CPURISCVState *env, uint32_t reg_index)
{
/* TODO: RV128 restriction check */
if ((reg_index & 1) && (riscv_cpu_mxl(env) == MXL_RV64)) {
return false;
}
return true;
}
static RISCVException read_pmpcfg(CPURISCVState *env, int csrno, static RISCVException read_pmpcfg(CPURISCVState *env, int csrno,
target_ulong *val) target_ulong *val)
{ {
uint32_t reg_index = csrno - CSR_PMPCFG0;
if (!check_pmp_reg_index(env, reg_index)) {
return RISCV_EXCP_ILLEGAL_INST;
}
*val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0); *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0);
return RISCV_EXCP_NONE; return RISCV_EXCP_NONE;
} }
@ -1507,6 +1521,11 @@ static RISCVException read_pmpcfg(CPURISCVState *env, int csrno,
static RISCVException write_pmpcfg(CPURISCVState *env, int csrno, static RISCVException write_pmpcfg(CPURISCVState *env, int csrno,
target_ulong val) target_ulong val)
{ {
uint32_t reg_index = csrno - CSR_PMPCFG0;
if (!check_pmp_reg_index(env, reg_index)) {
return RISCV_EXCP_ILLEGAL_INST;
}
pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val); pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val);
return RISCV_EXCP_NONE; return RISCV_EXCP_NONE;
} }

12
target/riscv/pmp.c
View file

@ -463,16 +463,11 @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
{ {
int i; int i;
uint8_t cfg_val; uint8_t cfg_val;
int pmpcfg_nums = 2 << riscv_cpu_mxl(env);
trace_pmpcfg_csr_write(env->mhartid, reg_index, val); trace_pmpcfg_csr_write(env->mhartid, reg_index, val);
if ((reg_index & 1) && (sizeof(target_ulong) == 8)) { for (i = 0; i < pmpcfg_nums; i++) {
qemu_log_mask(LOG_GUEST_ERROR,
"ignoring pmpcfg write - incorrect address\n");
return;
}
for (i = 0; i < sizeof(target_ulong); i++) {
cfg_val = (val >> 8 * i) & 0xff; cfg_val = (val >> 8 * i) & 0xff;
pmp_write_cfg(env, (reg_index * 4) + i, cfg_val); pmp_write_cfg(env, (reg_index * 4) + i, cfg_val);
} }
@ -490,8 +485,9 @@ target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index)
int i; int i;
target_ulong cfg_val = 0; target_ulong cfg_val = 0;
target_ulong val = 0; target_ulong val = 0;
int pmpcfg_nums = 2 << riscv_cpu_mxl(env);
for (i = 0; i < sizeof(target_ulong); i++) { for (i = 0; i < pmpcfg_nums; i++) {
val = pmp_read_cfg(env, (reg_index * 4) + i); val = pmp_read_cfg(env, (reg_index * 4) + i);
cfg_val |= (val << (i * 8)); cfg_val |= (val << (i * 8));
} }