mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-08 02:03:56 -06:00
generic VGA API layer
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@890 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard
parent
22a56b8a87
commit
798b0c25cc
2 changed files with 191 additions and 127 deletions
166
hw/vga.c
166
hw/vga.c
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@ -22,6 +22,7 @@
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* THE SOFTWARE.
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* THE SOFTWARE.
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*/
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*/
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#include "vl.h"
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#include "vl.h"
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#include "vga_int.h"
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//#define DEBUG_VGA
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//#define DEBUG_VGA
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//#define DEBUG_VGA_MEM
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//#define DEBUG_VGA_MEM
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@ -33,96 +34,8 @@
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/* S3 VGA is deprecated - another graphic card will be emulated */
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/* S3 VGA is deprecated - another graphic card will be emulated */
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//#define CONFIG_S3VGA
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//#define CONFIG_S3VGA
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#define MSR_COLOR_EMULATION 0x01
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#define MSR_PAGE_SELECT 0x20
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#define ST01_V_RETRACE 0x08
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#define ST01_DISP_ENABLE 0x01
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/* bochs VBE support */
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#define CONFIG_BOCHS_VBE
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#define VBE_DISPI_MAX_XRES 1024
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#define VBE_DISPI_MAX_YRES 768
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#define VBE_DISPI_INDEX_ID 0x0
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#define VBE_DISPI_INDEX_XRES 0x1
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#define VBE_DISPI_INDEX_YRES 0x2
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#define VBE_DISPI_INDEX_BPP 0x3
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#define VBE_DISPI_INDEX_ENABLE 0x4
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#define VBE_DISPI_INDEX_BANK 0x5
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#define VBE_DISPI_INDEX_VIRT_WIDTH 0x6
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#define VBE_DISPI_INDEX_VIRT_HEIGHT 0x7
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#define VBE_DISPI_INDEX_X_OFFSET 0x8
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#define VBE_DISPI_INDEX_Y_OFFSET 0x9
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#define VBE_DISPI_INDEX_NB 0xa
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#define VBE_DISPI_ID0 0xB0C0
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#define VBE_DISPI_ID1 0xB0C1
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#define VBE_DISPI_ID2 0xB0C2
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#define VBE_DISPI_DISABLED 0x00
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#define VBE_DISPI_ENABLED 0x01
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#define VBE_DISPI_LFB_ENABLED 0x40
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#define VBE_DISPI_NOCLEARMEM 0x80
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#define VBE_DISPI_LFB_PHYSICAL_ADDRESS 0xE0000000
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typedef struct VGAState {
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uint8_t *vram_ptr;
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unsigned long vram_offset;
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unsigned int vram_size;
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uint32_t latch;
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uint8_t sr_index;
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uint8_t sr[8];
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uint8_t gr_index;
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uint8_t gr[16];
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uint8_t ar_index;
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uint8_t ar[21];
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int ar_flip_flop;
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uint8_t cr_index;
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uint8_t cr[256]; /* CRT registers */
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uint8_t msr; /* Misc Output Register */
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uint8_t fcr; /* Feature Control Register */
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uint8_t st00; /* status 0 */
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uint8_t st01; /* status 1 */
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uint8_t dac_state;
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uint8_t dac_sub_index;
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uint8_t dac_read_index;
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uint8_t dac_write_index;
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uint8_t dac_cache[3]; /* used when writing */
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uint8_t palette[768];
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int32_t bank_offset;
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#ifdef CONFIG_BOCHS_VBE
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uint16_t vbe_index;
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uint16_t vbe_regs[VBE_DISPI_INDEX_NB];
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uint32_t vbe_start_addr;
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uint32_t vbe_line_offset;
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uint32_t vbe_bank_mask;
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#endif
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/* display refresh support */
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DisplayState *ds;
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uint32_t font_offsets[2];
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int graphic_mode;
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uint8_t shift_control;
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uint8_t double_scan;
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uint32_t line_offset;
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uint32_t line_compare;
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uint32_t start_addr;
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uint8_t last_cw, last_ch;
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uint32_t last_width, last_height; /* in chars or pixels */
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uint32_t last_scr_width, last_scr_height; /* in pixels */
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uint8_t cursor_start, cursor_end;
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uint32_t cursor_offset;
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unsigned int (*rgb_to_pixel)(unsigned int r, unsigned int g, unsigned b);
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/* tell for each page if it has been updated since the last time */
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uint32_t last_palette[256];
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#define CH_ATTR_SIZE (160 * 100)
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uint32_t last_ch_attr[CH_ATTR_SIZE]; /* XXX: make it dynamic */
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} VGAState;
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/* force some bits to zero */
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/* force some bits to zero */
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static const uint8_t sr_mask[8] = {
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const uint8_t sr_mask[8] = {
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(uint8_t)~0xfc,
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(uint8_t)~0xfc,
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(uint8_t)~0xc2,
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(uint8_t)~0xc2,
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(uint8_t)~0xf0,
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(uint8_t)~0xf0,
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@ -133,7 +46,7 @@ static const uint8_t sr_mask[8] = {
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(uint8_t)~0x00,
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(uint8_t)~0x00,
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};
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};
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static const uint8_t gr_mask[16] = {
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const uint8_t gr_mask[16] = {
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(uint8_t)~0xf0, /* 0x00 */
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(uint8_t)~0xf0, /* 0x00 */
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(uint8_t)~0xf0, /* 0x01 */
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(uint8_t)~0xf0, /* 0x01 */
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(uint8_t)~0xf0, /* 0x02 */
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(uint8_t)~0xf0, /* 0x02 */
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@ -656,7 +569,7 @@ static void vbe_ioport_write_data(void *opaque, uint32_t addr, uint32_t val)
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#endif
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#endif
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/* called for accesses between 0xa0000 and 0xc0000 */
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/* called for accesses between 0xa0000 and 0xc0000 */
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static uint32_t vga_mem_readb(void *opaque, target_phys_addr_t addr)
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uint32_t vga_mem_readb(void *opaque, target_phys_addr_t addr)
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{
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{
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VGAState *s = opaque;
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VGAState *s = opaque;
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int memory_map_mode, plane;
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int memory_map_mode, plane;
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@ -743,7 +656,7 @@ static uint32_t vga_mem_readl(void *opaque, target_phys_addr_t addr)
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}
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}
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/* called for accesses between 0xa0000 and 0xc0000 */
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/* called for accesses between 0xa0000 and 0xc0000 */
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static void vga_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
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void vga_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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{
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VGAState *s = opaque;
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VGAState *s = opaque;
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int memory_map_mode, plane, write_mode, b, func_select;
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int memory_map_mode, plane, write_mode, b, func_select;
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@ -1027,14 +940,11 @@ static int update_palette256(VGAState *s)
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return full_update;
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return full_update;
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}
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}
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/* update start_addr and line_offset. Return TRUE if modified */
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static void vga_get_offsets(VGAState *s,
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static int update_basic_params(VGAState *s)
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uint32_t *pline_offset,
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uint32_t *pstart_addr)
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{
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{
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int full_update;
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uint32_t start_addr, line_offset;
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uint32_t start_addr, line_offset, line_compare;
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full_update = 0;
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#ifdef CONFIG_BOCHS_VBE
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#ifdef CONFIG_BOCHS_VBE
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if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
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if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
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line_offset = s->vbe_line_offset;
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line_offset = s->vbe_line_offset;
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@ -1061,7 +971,19 @@ static int update_basic_params(VGAState *s)
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start_addr |= (s->cr[0x69] & 0x1f) << 16; /* S3 extension */
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start_addr |= (s->cr[0x69] & 0x1f) << 16; /* S3 extension */
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#endif
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#endif
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}
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}
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*pline_offset = line_offset;
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*pstart_addr = start_addr;
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}
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/* update start_addr and line_offset. Return TRUE if modified */
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static int update_basic_params(VGAState *s)
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{
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int full_update;
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uint32_t start_addr, line_offset, line_compare;
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full_update = 0;
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s->get_offsets(s, &line_offset, &start_addr);
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/* line compare */
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/* line compare */
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line_compare = s->cr[0x18] |
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line_compare = s->cr[0x18] |
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((s->cr[0x07] & 0x10) << 4) |
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((s->cr[0x07] & 0x10) << 4) |
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@ -1373,6 +1295,20 @@ static vga_draw_line_func *vga_draw_line_table[4 * VGA_DRAW_LINE_NB] = {
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vga_draw_line32_32,
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vga_draw_line32_32,
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};
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};
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static int vga_get_bpp(VGAState *s)
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{
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int ret;
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#ifdef CONFIG_BOCHS_VBE
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if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
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ret = s->vbe_regs[VBE_DISPI_INDEX_BPP];
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} else
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#endif
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{
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ret = 0;
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}
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return ret;
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}
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/*
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/*
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* graphic modes
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* graphic modes
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* Missing:
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* Missing:
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@ -1429,10 +1365,12 @@ static void vga_draw_graphic(VGAState *s, int full_update)
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v = VGA_DRAW_LINE2;
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v = VGA_DRAW_LINE2;
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}
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}
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} else {
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} else {
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#ifdef CONFIG_BOCHS_VBE
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switch(s->get_bpp(s)) {
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if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
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switch(s->vbe_regs[VBE_DISPI_INDEX_BPP]) {
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default:
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default:
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case 0:
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full_update |= update_palette256(s);
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v = VGA_DRAW_LINE8D2;
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break;
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case 8:
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case 8:
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full_update |= update_palette256(s);
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full_update |= update_palette256(s);
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v = VGA_DRAW_LINE8;
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v = VGA_DRAW_LINE8;
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@ -1450,12 +1388,6 @@ static void vga_draw_graphic(VGAState *s, int full_update)
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v = VGA_DRAW_LINE32;
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v = VGA_DRAW_LINE32;
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break;
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break;
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}
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}
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} else
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#endif
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{
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full_update |= update_palette256(s);
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v = VGA_DRAW_LINE8D2;
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}
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}
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}
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vga_draw_line = vga_draw_line_table[v * 4 + get_depth_index(s->ds->depth)];
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vga_draw_line = vga_draw_line_table[v * 4 + get_depth_index(s->ds->depth)];
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@ -1747,11 +1679,9 @@ static void vga_map(PCIDevice *pci_dev, int region_num,
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cpu_register_physical_memory(addr, s->vram_size, s->vram_offset);
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cpu_register_physical_memory(addr, s->vram_size, s->vram_offset);
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}
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}
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int vga_initialize(DisplayState *ds, uint8_t *vga_ram_base,
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void vga_common_init(VGAState *s, DisplayState *ds, uint8_t *vga_ram_base,
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unsigned long vga_ram_offset, int vga_ram_size,
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unsigned long vga_ram_offset, int vga_ram_size)
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int is_pci)
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{
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{
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VGAState *s = &vga_state;
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int i, j, v, b;
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int i, j, v, b;
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for(i = 0;i < 256; i++) {
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for(i = 0;i < 256; i++) {
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@ -1783,6 +1713,18 @@ int vga_initialize(DisplayState *ds, uint8_t *vga_ram_base,
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s->vram_offset = vga_ram_offset;
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s->vram_offset = vga_ram_offset;
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s->vram_size = vga_ram_size;
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s->vram_size = vga_ram_size;
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s->ds = ds;
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s->ds = ds;
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s->get_bpp = vga_get_bpp;
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s->get_offsets = vga_get_offsets;
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}
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int vga_initialize(DisplayState *ds, uint8_t *vga_ram_base,
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unsigned long vga_ram_offset, int vga_ram_size,
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int is_pci)
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{
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VGAState *s = &vga_state;
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vga_common_init(s, ds, vga_ram_base, vga_ram_offset, vga_ram_size);
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register_savevm("vga", 0, 1, vga_save, vga_load, s);
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register_savevm("vga", 0, 1, vga_save, vga_load, s);
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122
hw/vga_int.h
Normal file
122
hw/vga_int.h
Normal file
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@ -0,0 +1,122 @@
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/*
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* QEMU internal VGA defines.
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*
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* Copyright (c) 2003-2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#define MSR_COLOR_EMULATION 0x01
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#define MSR_PAGE_SELECT 0x20
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#define ST01_V_RETRACE 0x08
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#define ST01_DISP_ENABLE 0x01
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/* bochs VBE support */
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#define CONFIG_BOCHS_VBE
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#define VBE_DISPI_MAX_XRES 1024
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#define VBE_DISPI_MAX_YRES 768
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#define VBE_DISPI_INDEX_ID 0x0
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#define VBE_DISPI_INDEX_XRES 0x1
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#define VBE_DISPI_INDEX_YRES 0x2
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#define VBE_DISPI_INDEX_BPP 0x3
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#define VBE_DISPI_INDEX_ENABLE 0x4
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#define VBE_DISPI_INDEX_BANK 0x5
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#define VBE_DISPI_INDEX_VIRT_WIDTH 0x6
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#define VBE_DISPI_INDEX_VIRT_HEIGHT 0x7
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#define VBE_DISPI_INDEX_X_OFFSET 0x8
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#define VBE_DISPI_INDEX_Y_OFFSET 0x9
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#define VBE_DISPI_INDEX_NB 0xa
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#define VBE_DISPI_ID0 0xB0C0
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#define VBE_DISPI_ID1 0xB0C1
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#define VBE_DISPI_ID2 0xB0C2
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#define VBE_DISPI_DISABLED 0x00
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#define VBE_DISPI_ENABLED 0x01
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#define VBE_DISPI_LFB_ENABLED 0x40
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#define VBE_DISPI_NOCLEARMEM 0x80
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#define VBE_DISPI_LFB_PHYSICAL_ADDRESS 0xE0000000
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typedef struct VGAState {
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uint8_t *vram_ptr;
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unsigned long vram_offset;
|
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|
unsigned int vram_size;
|
||||||
|
uint32_t latch;
|
||||||
|
uint8_t sr_index;
|
||||||
|
uint8_t sr[256];
|
||||||
|
uint8_t gr_index;
|
||||||
|
uint8_t gr[256];
|
||||||
|
uint8_t ar_index;
|
||||||
|
uint8_t ar[21];
|
||||||
|
int ar_flip_flop;
|
||||||
|
uint8_t cr_index;
|
||||||
|
uint8_t cr[256]; /* CRT registers */
|
||||||
|
uint8_t msr; /* Misc Output Register */
|
||||||
|
uint8_t fcr; /* Feature Control Register */
|
||||||
|
uint8_t st00; /* status 0 */
|
||||||
|
uint8_t st01; /* status 1 */
|
||||||
|
uint8_t dac_state;
|
||||||
|
uint8_t dac_sub_index;
|
||||||
|
uint8_t dac_read_index;
|
||||||
|
uint8_t dac_write_index;
|
||||||
|
uint8_t dac_cache[3]; /* used when writing */
|
||||||
|
uint8_t palette[768];
|
||||||
|
int32_t bank_offset;
|
||||||
|
int (*get_bpp)(struct VGAState *s);
|
||||||
|
void (*get_offsets)(struct VGAState *s,
|
||||||
|
uint32_t *pline_offset,
|
||||||
|
uint32_t *pstart_addr);
|
||||||
|
#ifdef CONFIG_BOCHS_VBE
|
||||||
|
uint16_t vbe_index;
|
||||||
|
uint16_t vbe_regs[VBE_DISPI_INDEX_NB];
|
||||||
|
uint32_t vbe_start_addr;
|
||||||
|
uint32_t vbe_line_offset;
|
||||||
|
uint32_t vbe_bank_mask;
|
||||||
|
#endif
|
||||||
|
/* display refresh support */
|
||||||
|
DisplayState *ds;
|
||||||
|
uint32_t font_offsets[2];
|
||||||
|
int graphic_mode;
|
||||||
|
uint8_t shift_control;
|
||||||
|
uint8_t double_scan;
|
||||||
|
uint32_t line_offset;
|
||||||
|
uint32_t line_compare;
|
||||||
|
uint32_t start_addr;
|
||||||
|
uint8_t last_cw, last_ch;
|
||||||
|
uint32_t last_width, last_height; /* in chars or pixels */
|
||||||
|
uint32_t last_scr_width, last_scr_height; /* in pixels */
|
||||||
|
uint8_t cursor_start, cursor_end;
|
||||||
|
uint32_t cursor_offset;
|
||||||
|
unsigned int (*rgb_to_pixel)(unsigned int r, unsigned int g, unsigned b);
|
||||||
|
/* tell for each page if it has been updated since the last time */
|
||||||
|
uint32_t last_palette[256];
|
||||||
|
#define CH_ATTR_SIZE (160 * 100)
|
||||||
|
uint32_t last_ch_attr[CH_ATTR_SIZE]; /* XXX: make it dynamic */
|
||||||
|
} VGAState;
|
||||||
|
|
||||||
|
void vga_common_init(VGAState *s, DisplayState *ds, uint8_t *vga_ram_base,
|
||||||
|
unsigned long vga_ram_offset, int vga_ram_size);
|
||||||
|
uint32_t vga_mem_readb(void *opaque, target_phys_addr_t addr);
|
||||||
|
void vga_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val);
|
||||||
|
|
||||||
|
extern const uint8_t sr_mask[8];
|
||||||
|
extern const uint8_t gr_mask[16];
|
||||||
Loading…
Add table
Add a link
Reference in a new issue