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target/riscv: rvv-1.0: stride load and store instructions
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-21-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Frank Chang
Alistair Francis
parent
d9b7609a1f
commit
79556fb6fa
4 changed files with 290 additions and 437 deletions
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@ -73,6 +73,12 @@ static bool require_vm(int vm, int vd)
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return (vm != 0 || vd != 0);
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}
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static bool require_nf(int vd, int nf, int lmul)
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{
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int size = nf << MAX(lmul, 0);
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return size <= 8 && vd + size <= 32;
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}
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/*
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* Vector register should aligned with the passed-in LMUL (EMUL).
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* If LMUL < 0, i.e. fractional LMUL, any vector register is allowed.
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@ -175,6 +181,115 @@ static uint32_t vreg_ofs(DisasContext *s, int reg)
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/* check functions */
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/*
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* Vector unit-stride, strided, unit-stride segment, strided segment
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* store check function.
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*
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* Rules to be checked here:
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* 1. EMUL must within the range: 1/8 <= EMUL <= 8. (Section 7.3)
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* 2. Destination vector register number is multiples of EMUL.
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* (Section 3.4.2, 7.3)
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* 3. The EMUL setting must be such that EMUL * NFIELDS ≤ 8. (Section 7.8)
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* 4. Vector register numbers accessed by the segment load or store
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* cannot increment past 31. (Section 7.8)
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*/
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static bool vext_check_store(DisasContext *s, int vd, int nf, uint8_t eew)
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{
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int8_t emul = eew - s->sew + s->lmul;
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return (emul >= -3 && emul <= 3) &&
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require_align(vd, emul) &&
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require_nf(vd, nf, emul);
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}
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/*
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* Vector unit-stride, strided, unit-stride segment, strided segment
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* load check function.
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*
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* Rules to be checked here:
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* 1. All rules applies to store instructions are applies
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* to load instructions.
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* 2. Destination vector register group for a masked vector
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* instruction cannot overlap the source mask register (v0).
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* (Section 5.3)
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*/
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static bool vext_check_load(DisasContext *s, int vd, int nf, int vm,
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uint8_t eew)
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{
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return vext_check_store(s, vd, nf, eew) && require_vm(vm, vd);
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}
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/*
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* Vector indexed, indexed segment store check function.
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*
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* Rules to be checked here:
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* 1. EMUL must within the range: 1/8 <= EMUL <= 8. (Section 7.3)
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* 2. Index vector register number is multiples of EMUL.
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* (Section 3.4.2, 7.3)
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* 3. Destination vector register number is multiples of LMUL.
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* (Section 3.4.2, 7.3)
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* 4. The EMUL setting must be such that EMUL * NFIELDS ≤ 8. (Section 7.8)
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* 5. Vector register numbers accessed by the segment load or store
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* cannot increment past 31. (Section 7.8)
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*/
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static bool vext_check_st_index(DisasContext *s, int vd, int vs2, int nf,
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uint8_t eew)
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{
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int8_t emul = eew - s->sew + s->lmul;
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return (emul >= -3 && emul <= 3) &&
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require_align(vs2, emul) &&
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require_align(vd, s->lmul) &&
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require_nf(vd, nf, s->lmul);
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}
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/*
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* Vector indexed, indexed segment load check function.
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*
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* Rules to be checked here:
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* 1. All rules applies to store instructions are applies
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* to load instructions.
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* 2. Destination vector register group for a masked vector
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* instruction cannot overlap the source mask register (v0).
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* (Section 5.3)
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* 3. Destination vector register cannot overlap a source vector
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* register (vs2) group.
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* (Section 5.2)
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* 4. Destination vector register groups cannot overlap
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* the source vector register (vs2) group for
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* indexed segment load instructions. (Section 7.8.3)
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*/
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static bool vext_check_ld_index(DisasContext *s, int vd, int vs2,
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int nf, int vm, uint8_t eew)
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{
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int8_t seg_vd;
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int8_t emul = eew - s->sew + s->lmul;
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bool ret = vext_check_st_index(s, vd, vs2, nf, eew) &&
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require_vm(vm, vd);
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/* Each segment register group has to follow overlap rules. */
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for (int i = 0; i < nf; ++i) {
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seg_vd = vd + (1 << MAX(s->lmul, 0)) * i;
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if (eew > s->sew) {
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if (seg_vd != vs2) {
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ret &= require_noover(seg_vd, s->lmul, vs2, emul);
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}
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} else if (eew < s->sew) {
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ret &= require_noover(seg_vd, s->lmul, vs2, emul);
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}
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/*
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* Destination vector register groups cannot overlap
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* the source vector register (vs2) group for
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* indexed segment load instructions.
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*/
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if (nf > 1) {
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ret &= !is_overlapped(seg_vd, 1 << MAX(s->lmul, 0),
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vs2, 1 << MAX(emul, 0));
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}
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}
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return ret;
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}
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static bool vext_check_ss(DisasContext *s, int vd, int vs, int vm)
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{
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return require_vm(vm, vd) &&
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@ -415,63 +530,14 @@ static bool vext_check_isa_ill(DisasContext *s)
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return !s->vill;
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}
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/*
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* There are two rules check here.
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*
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* 1. Vector register numbers are multiples of LMUL. (Section 3.2)
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*
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* 2. For all widening instructions, the destination LMUL value must also be
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* a supported LMUL value. (Section 11.2)
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*/
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static bool vext_check_reg(DisasContext *s, uint32_t reg, bool widen)
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{
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/*
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* The destination vector register group results are arranged as if both
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* SEW and LMUL were at twice their current settings. (Section 11.2).
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*/
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int legal = widen ? 2 << s->lmul : 1 << s->lmul;
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return !((s->lmul == 0x3 && widen) || (reg % legal));
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}
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/*
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* There are two rules check here.
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*
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* 1. The destination vector register group for a masked vector instruction can
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* only overlap the source mask register (v0) when LMUL=1. (Section 5.3)
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*
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* 2. In widen instructions and some other insturctions, like vslideup.vx,
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* there is no need to check whether LMUL=1.
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*/
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static bool vext_check_overlap_mask(DisasContext *s, uint32_t vd, bool vm,
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bool force)
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{
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return (vm != 0 || vd != 0) || (!force && (s->lmul == 0));
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}
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/* The LMUL setting must be such that LMUL * NFIELDS <= 8. (Section 7.8) */
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static bool vext_check_nf(DisasContext *s, uint32_t nf)
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{
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return (1 << s->lmul) * nf <= 8;
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}
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/*
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* The destination vector register group cannot overlap a source vector register
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* group of a different element width. (Section 11.2)
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*/
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static inline bool vext_check_overlap_group(int rd, int dlen, int rs, int slen)
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{
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return ((rd >= rs + slen) || (rs >= rd + dlen));
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}
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/* common translation macro */
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#define GEN_VEXT_TRANS(NAME, SEQ, ARGTYPE, OP, CHECK) \
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static bool trans_##NAME(DisasContext *s, arg_##ARGTYPE *a)\
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{ \
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if (CHECK(s, a)) { \
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return OP(s, a, SEQ); \
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} \
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return false; \
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#define GEN_VEXT_TRANS(NAME, EEW, ARGTYPE, OP, CHECK) \
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static bool trans_##NAME(DisasContext *s, arg_##ARGTYPE * a) \
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{ \
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if (CHECK(s, a, EEW)) { \
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return OP(s, a, EEW); \
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} \
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return false; \
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}
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/*
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@ -520,44 +586,20 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
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return true;
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}
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static bool ld_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
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static bool ld_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t eew)
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{
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uint32_t data = 0;
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gen_helper_ldst_us *fn;
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static gen_helper_ldst_us * const fns[2][7][4] = {
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static gen_helper_ldst_us * const fns[2][4] = {
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/* masked unit stride load */
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{ { gen_helper_vlb_v_b_mask, gen_helper_vlb_v_h_mask,
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gen_helper_vlb_v_w_mask, gen_helper_vlb_v_d_mask },
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{ NULL, gen_helper_vlh_v_h_mask,
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gen_helper_vlh_v_w_mask, gen_helper_vlh_v_d_mask },
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{ NULL, NULL,
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gen_helper_vlw_v_w_mask, gen_helper_vlw_v_d_mask },
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{ gen_helper_vle_v_b_mask, gen_helper_vle_v_h_mask,
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gen_helper_vle_v_w_mask, gen_helper_vle_v_d_mask },
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{ gen_helper_vlbu_v_b_mask, gen_helper_vlbu_v_h_mask,
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gen_helper_vlbu_v_w_mask, gen_helper_vlbu_v_d_mask },
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{ NULL, gen_helper_vlhu_v_h_mask,
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gen_helper_vlhu_v_w_mask, gen_helper_vlhu_v_d_mask },
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{ NULL, NULL,
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gen_helper_vlwu_v_w_mask, gen_helper_vlwu_v_d_mask } },
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{ gen_helper_vle8_v_mask, gen_helper_vle16_v_mask,
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gen_helper_vle32_v_mask, gen_helper_vle64_v_mask },
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/* unmasked unit stride load */
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{ { gen_helper_vlb_v_b, gen_helper_vlb_v_h,
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gen_helper_vlb_v_w, gen_helper_vlb_v_d },
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{ NULL, gen_helper_vlh_v_h,
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gen_helper_vlh_v_w, gen_helper_vlh_v_d },
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{ NULL, NULL,
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gen_helper_vlw_v_w, gen_helper_vlw_v_d },
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{ gen_helper_vle_v_b, gen_helper_vle_v_h,
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gen_helper_vle_v_w, gen_helper_vle_v_d },
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{ gen_helper_vlbu_v_b, gen_helper_vlbu_v_h,
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gen_helper_vlbu_v_w, gen_helper_vlbu_v_d },
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{ NULL, gen_helper_vlhu_v_h,
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gen_helper_vlhu_v_w, gen_helper_vlhu_v_d },
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{ NULL, NULL,
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gen_helper_vlwu_v_w, gen_helper_vlwu_v_d } }
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{ gen_helper_vle8_v, gen_helper_vle16_v,
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gen_helper_vle32_v, gen_helper_vle64_v }
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};
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fn = fns[a->vm][seq][s->sew];
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fn = fns[a->vm][eew];
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if (fn == NULL) {
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return false;
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}
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@ -568,48 +610,32 @@ static bool ld_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
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return ldst_us_trans(a->rd, a->rs1, data, fn, s, false);
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}
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static bool ld_us_check(DisasContext *s, arg_r2nfvm* a)
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static bool ld_us_check(DisasContext *s, arg_r2nfvm* a, uint8_t eew)
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{
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return (vext_check_isa_ill(s) &&
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vext_check_overlap_mask(s, a->rd, a->vm, false) &&
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vext_check_reg(s, a->rd, false) &&
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vext_check_nf(s, a->nf));
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return require_rvv(s) &&
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vext_check_isa_ill(s) &&
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vext_check_load(s, a->rd, a->nf, a->vm, eew);
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}
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GEN_VEXT_TRANS(vlb_v, 0, r2nfvm, ld_us_op, ld_us_check)
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GEN_VEXT_TRANS(vlh_v, 1, r2nfvm, ld_us_op, ld_us_check)
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GEN_VEXT_TRANS(vlw_v, 2, r2nfvm, ld_us_op, ld_us_check)
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GEN_VEXT_TRANS(vle_v, 3, r2nfvm, ld_us_op, ld_us_check)
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GEN_VEXT_TRANS(vlbu_v, 4, r2nfvm, ld_us_op, ld_us_check)
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GEN_VEXT_TRANS(vlhu_v, 5, r2nfvm, ld_us_op, ld_us_check)
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GEN_VEXT_TRANS(vlwu_v, 6, r2nfvm, ld_us_op, ld_us_check)
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GEN_VEXT_TRANS(vle8_v, MO_8, r2nfvm, ld_us_op, ld_us_check)
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GEN_VEXT_TRANS(vle16_v, MO_16, r2nfvm, ld_us_op, ld_us_check)
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GEN_VEXT_TRANS(vle32_v, MO_32, r2nfvm, ld_us_op, ld_us_check)
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GEN_VEXT_TRANS(vle64_v, MO_64, r2nfvm, ld_us_op, ld_us_check)
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static bool st_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
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static bool st_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t eew)
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{
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uint32_t data = 0;
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gen_helper_ldst_us *fn;
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static gen_helper_ldst_us * const fns[2][4][4] = {
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/* masked unit stride load and store */
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{ { gen_helper_vsb_v_b_mask, gen_helper_vsb_v_h_mask,
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gen_helper_vsb_v_w_mask, gen_helper_vsb_v_d_mask },
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{ NULL, gen_helper_vsh_v_h_mask,
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gen_helper_vsh_v_w_mask, gen_helper_vsh_v_d_mask },
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{ NULL, NULL,
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gen_helper_vsw_v_w_mask, gen_helper_vsw_v_d_mask },
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{ gen_helper_vse_v_b_mask, gen_helper_vse_v_h_mask,
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gen_helper_vse_v_w_mask, gen_helper_vse_v_d_mask } },
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static gen_helper_ldst_us * const fns[2][4] = {
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/* masked unit stride store */
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{ gen_helper_vse8_v_mask, gen_helper_vse16_v_mask,
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gen_helper_vse32_v_mask, gen_helper_vse64_v_mask },
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/* unmasked unit stride store */
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{ { gen_helper_vsb_v_b, gen_helper_vsb_v_h,
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gen_helper_vsb_v_w, gen_helper_vsb_v_d },
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{ NULL, gen_helper_vsh_v_h,
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gen_helper_vsh_v_w, gen_helper_vsh_v_d },
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{ NULL, NULL,
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gen_helper_vsw_v_w, gen_helper_vsw_v_d },
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{ gen_helper_vse_v_b, gen_helper_vse_v_h,
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gen_helper_vse_v_w, gen_helper_vse_v_d } }
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{ gen_helper_vse8_v, gen_helper_vse16_v,
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gen_helper_vse32_v, gen_helper_vse64_v }
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};
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fn = fns[a->vm][seq][s->sew];
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fn = fns[a->vm][eew];
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if (fn == NULL) {
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return false;
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}
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@ -620,17 +646,17 @@ static bool st_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
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return ldst_us_trans(a->rd, a->rs1, data, fn, s, true);
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}
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static bool st_us_check(DisasContext *s, arg_r2nfvm* a)
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static bool st_us_check(DisasContext *s, arg_r2nfvm* a, uint8_t eew)
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{
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return (vext_check_isa_ill(s) &&
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vext_check_reg(s, a->rd, false) &&
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vext_check_nf(s, a->nf));
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return require_rvv(s) &&
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vext_check_isa_ill(s) &&
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vext_check_store(s, a->rd, a->nf, eew);
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}
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GEN_VEXT_TRANS(vsb_v, 0, r2nfvm, st_us_op, st_us_check)
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GEN_VEXT_TRANS(vsh_v, 1, r2nfvm, st_us_op, st_us_check)
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GEN_VEXT_TRANS(vsw_v, 2, r2nfvm, st_us_op, st_us_check)
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GEN_VEXT_TRANS(vse_v, 3, r2nfvm, st_us_op, st_us_check)
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GEN_VEXT_TRANS(vse8_v, MO_8, r2nfvm, st_us_op, st_us_check)
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GEN_VEXT_TRANS(vse16_v, MO_16, r2nfvm, st_us_op, st_us_check)
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GEN_VEXT_TRANS(vse32_v, MO_32, r2nfvm, st_us_op, st_us_check)
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GEN_VEXT_TRANS(vse64_v, MO_64, r2nfvm, st_us_op, st_us_check)
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/*
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*** stride load and store
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@ -671,28 +697,16 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
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return true;
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}
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static bool ld_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
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static bool ld_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)
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{
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uint32_t data = 0;
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gen_helper_ldst_stride *fn;
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static gen_helper_ldst_stride * const fns[7][4] = {
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{ gen_helper_vlsb_v_b, gen_helper_vlsb_v_h,
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gen_helper_vlsb_v_w, gen_helper_vlsb_v_d },
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{ NULL, gen_helper_vlsh_v_h,
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gen_helper_vlsh_v_w, gen_helper_vlsh_v_d },
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{ NULL, NULL,
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gen_helper_vlsw_v_w, gen_helper_vlsw_v_d },
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{ gen_helper_vlse_v_b, gen_helper_vlse_v_h,
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gen_helper_vlse_v_w, gen_helper_vlse_v_d },
|
||||
{ gen_helper_vlsbu_v_b, gen_helper_vlsbu_v_h,
|
||||
gen_helper_vlsbu_v_w, gen_helper_vlsbu_v_d },
|
||||
{ NULL, gen_helper_vlshu_v_h,
|
||||
gen_helper_vlshu_v_w, gen_helper_vlshu_v_d },
|
||||
{ NULL, NULL,
|
||||
gen_helper_vlswu_v_w, gen_helper_vlswu_v_d },
|
||||
static gen_helper_ldst_stride * const fns[4] = {
|
||||
gen_helper_vlse8_v, gen_helper_vlse16_v,
|
||||
gen_helper_vlse32_v, gen_helper_vlse64_v
|
||||
};
|
||||
|
||||
fn = fns[seq][s->sew];
|
||||
fn = fns[eew];
|
||||
if (fn == NULL) {
|
||||
return false;
|
||||
}
|
||||
|
|
@ -703,42 +717,32 @@ static bool ld_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
|
|||
return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s, false);
|
||||
}
|
||||
|
||||
static bool ld_stride_check(DisasContext *s, arg_rnfvm* a)
|
||||
static bool ld_stride_check(DisasContext *s, arg_rnfvm* a, uint8_t eew)
|
||||
{
|
||||
return (vext_check_isa_ill(s) &&
|
||||
vext_check_overlap_mask(s, a->rd, a->vm, false) &&
|
||||
vext_check_reg(s, a->rd, false) &&
|
||||
vext_check_nf(s, a->nf));
|
||||
return require_rvv(s) &&
|
||||
vext_check_isa_ill(s) &&
|
||||
vext_check_load(s, a->rd, a->nf, a->vm, eew);
|
||||
}
|
||||
|
||||
GEN_VEXT_TRANS(vlsb_v, 0, rnfvm, ld_stride_op, ld_stride_check)
|
||||
GEN_VEXT_TRANS(vlsh_v, 1, rnfvm, ld_stride_op, ld_stride_check)
|
||||
GEN_VEXT_TRANS(vlsw_v, 2, rnfvm, ld_stride_op, ld_stride_check)
|
||||
GEN_VEXT_TRANS(vlse_v, 3, rnfvm, ld_stride_op, ld_stride_check)
|
||||
GEN_VEXT_TRANS(vlsbu_v, 4, rnfvm, ld_stride_op, ld_stride_check)
|
||||
GEN_VEXT_TRANS(vlshu_v, 5, rnfvm, ld_stride_op, ld_stride_check)
|
||||
GEN_VEXT_TRANS(vlswu_v, 6, rnfvm, ld_stride_op, ld_stride_check)
|
||||
GEN_VEXT_TRANS(vlse8_v, MO_8, rnfvm, ld_stride_op, ld_stride_check)
|
||||
GEN_VEXT_TRANS(vlse16_v, MO_16, rnfvm, ld_stride_op, ld_stride_check)
|
||||
GEN_VEXT_TRANS(vlse32_v, MO_32, rnfvm, ld_stride_op, ld_stride_check)
|
||||
GEN_VEXT_TRANS(vlse64_v, MO_64, rnfvm, ld_stride_op, ld_stride_check)
|
||||
|
||||
static bool st_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
|
||||
static bool st_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)
|
||||
{
|
||||
uint32_t data = 0;
|
||||
gen_helper_ldst_stride *fn;
|
||||
static gen_helper_ldst_stride * const fns[4][4] = {
|
||||
static gen_helper_ldst_stride * const fns[4] = {
|
||||
/* masked stride store */
|
||||
{ gen_helper_vssb_v_b, gen_helper_vssb_v_h,
|
||||
gen_helper_vssb_v_w, gen_helper_vssb_v_d },
|
||||
{ NULL, gen_helper_vssh_v_h,
|
||||
gen_helper_vssh_v_w, gen_helper_vssh_v_d },
|
||||
{ NULL, NULL,
|
||||
gen_helper_vssw_v_w, gen_helper_vssw_v_d },
|
||||
{ gen_helper_vsse_v_b, gen_helper_vsse_v_h,
|
||||
gen_helper_vsse_v_w, gen_helper_vsse_v_d }
|
||||
gen_helper_vsse8_v, gen_helper_vsse16_v,
|
||||
gen_helper_vsse32_v, gen_helper_vsse64_v
|
||||
};
|
||||
|
||||
data = FIELD_DP32(data, VDATA, VM, a->vm);
|
||||
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
|
||||
data = FIELD_DP32(data, VDATA, NF, a->nf);
|
||||
fn = fns[seq][s->sew];
|
||||
fn = fns[eew];
|
||||
if (fn == NULL) {
|
||||
return false;
|
||||
}
|
||||
|
|
@ -746,17 +750,17 @@ static bool st_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
|
|||
return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s, true);
|
||||
}
|
||||
|
||||
static bool st_stride_check(DisasContext *s, arg_rnfvm* a)
|
||||
static bool st_stride_check(DisasContext *s, arg_rnfvm* a, uint8_t eew)
|
||||
{
|
||||
return (vext_check_isa_ill(s) &&
|
||||
vext_check_reg(s, a->rd, false) &&
|
||||
vext_check_nf(s, a->nf));
|
||||
return require_rvv(s) &&
|
||||
vext_check_isa_ill(s) &&
|
||||
vext_check_store(s, a->rd, a->nf, eew);
|
||||
}
|
||||
|
||||
GEN_VEXT_TRANS(vssb_v, 0, rnfvm, st_stride_op, st_stride_check)
|
||||
GEN_VEXT_TRANS(vssh_v, 1, rnfvm, st_stride_op, st_stride_check)
|
||||
GEN_VEXT_TRANS(vssw_v, 2, rnfvm, st_stride_op, st_stride_check)
|
||||
GEN_VEXT_TRANS(vsse_v, 3, rnfvm, st_stride_op, st_stride_check)
|
||||
GEN_VEXT_TRANS(vsse8_v, MO_8, rnfvm, st_stride_op, st_stride_check)
|
||||
GEN_VEXT_TRANS(vsse16_v, MO_16, rnfvm, st_stride_op, st_stride_check)
|
||||
GEN_VEXT_TRANS(vsse32_v, MO_32, rnfvm, st_stride_op, st_stride_check)
|
||||
GEN_VEXT_TRANS(vsse64_v, MO_64, rnfvm, st_stride_op, st_stride_check)
|
||||
|
||||
/*
|
||||
*** index load and store
|
||||
|
|
@ -836,16 +840,11 @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
|
|||
* groups cannot overlap the source vector register group (specified by
|
||||
* `vs2`), else an illegal instruction exception is raised.
|
||||
*/
|
||||
static bool ld_index_check(DisasContext *s, arg_rnfvm* a)
|
||||
static bool ld_index_check(DisasContext *s, arg_rnfvm* a, uint8_t eew)
|
||||
{
|
||||
return (vext_check_isa_ill(s) &&
|
||||
vext_check_overlap_mask(s, a->rd, a->vm, false) &&
|
||||
vext_check_reg(s, a->rd, false) &&
|
||||
vext_check_reg(s, a->rs2, false) &&
|
||||
vext_check_nf(s, a->nf) &&
|
||||
((a->nf == 1) ||
|
||||
vext_check_overlap_group(a->rd, a->nf << s->lmul,
|
||||
a->rs2, 1 << s->lmul)));
|
||||
return require_rvv(s) &&
|
||||
vext_check_isa_ill(s) &&
|
||||
vext_check_ld_index(s, a->rd, a->rs2, a->nf, a->vm, eew);
|
||||
}
|
||||
|
||||
GEN_VEXT_TRANS(vlxb_v, 0, rnfvm, ld_index_op, ld_index_check)
|
||||
|
|
@ -882,12 +881,11 @@ static bool st_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
|
|||
return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, true);
|
||||
}
|
||||
|
||||
static bool st_index_check(DisasContext *s, arg_rnfvm* a)
|
||||
static bool st_index_check(DisasContext *s, arg_rnfvm* a, uint8_t eew)
|
||||
{
|
||||
return (vext_check_isa_ill(s) &&
|
||||
vext_check_reg(s, a->rd, false) &&
|
||||
vext_check_reg(s, a->rs2, false) &&
|
||||
vext_check_nf(s, a->nf));
|
||||
return require_rvv(s) &&
|
||||
vext_check_isa_ill(s) &&
|
||||
vext_check_st_index(s, a->rd, a->rs2, a->nf, eew);
|
||||
}
|
||||
|
||||
GEN_VEXT_TRANS(vsxb_v, 0, rnfvm, st_index_op, st_index_check)
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue