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intel_iommu: Add a placeholder variable for scalable mode stage-1 translation

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Add an new element flts in IntelIOMMUState to mark stage-1 translation support
in scalable mode, this element will be exposed as an intel_iommu property
x-flts finally.

For now, it's only a placehholder and used for address width compatibility
check and block host device passthrough until nesting is supported.

Signed-off-by: Yi Liu <yi.l.liu@intel.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com>
Reviewed-by: Yi Liu <yi.l.liu@intel.com>
Message-Id: <20241212083757.605022-4-zhenzhong.duan@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Zhenzhong Duan 2024-12-12 16:37:40 +08:00 • committed by Michael S. Tsirkin
parent b291dae33d
commit 791346f93d
2 changed files with 19 additions and 5 deletions
Download patch file Download diff file Expand all files Collapse all files

21
hw/i386/intel_iommu.c
View file

@ -3917,7 +3917,13 @@ static bool vtd_check_hiod(IntelIOMMUState *s, HostIOMMUDevice *hiod,
return false; return false;
} }
if (!s->flts) {
/* All checks requested by VTD stage-2 translation pass */
return true; return true;
}
error_setg(errp, "host device is uncompatible with stage-1 translation");
return false;
} }
static bool vtd_dev_set_iommu_device(PCIBus *bus, void *opaque, int devfn, static bool vtd_dev_set_iommu_device(PCIBus *bus, void *opaque, int devfn,
@ -4307,14 +4313,21 @@ static bool vtd_decide_config(IntelIOMMUState *s, Error **errp)
} }
} }
/* Currently only address widths supported are 39 and 48 bits */ if (!s->flts && s->aw_bits != VTD_HOST_AW_39BIT &&
if ((s->aw_bits != VTD_HOST_AW_39BIT) && s->aw_bits != VTD_HOST_AW_48BIT) {
(s->aw_bits != VTD_HOST_AW_48BIT)) { error_setg(errp, "%s: supported values for aw-bits are: %d, %d",
error_setg(errp, "Supported values for aw-bits are: %d, %d", s->scalable_mode ? "Scalable mode(flts=off)" : "Legacy mode",
VTD_HOST_AW_39BIT, VTD_HOST_AW_48BIT); VTD_HOST_AW_39BIT, VTD_HOST_AW_48BIT);
return false; return false;
} }
if (s->flts && s->aw_bits != VTD_HOST_AW_48BIT) {
error_setg(errp,
"Scalable mode(flts=on): supported value for aw-bits is: %d",
VTD_HOST_AW_48BIT);
return false;
}
if (s->scalable_mode && !s->dma_drain) { if (s->scalable_mode && !s->dma_drain) {
error_setg(errp, "Need to set dma_drain for scalable mode"); error_setg(errp, "Need to set dma_drain for scalable mode");
return false; return false;

1
include/hw/i386/intel_iommu.h
View file

@ -262,6 +262,7 @@ struct IntelIOMMUState {
bool caching_mode; /* RO - is cap CM enabled? */ bool caching_mode; /* RO - is cap CM enabled? */
bool scalable_mode; /* RO - is Scalable Mode supported? */ bool scalable_mode; /* RO - is Scalable Mode supported? */
bool flts; /* RO - is stage-1 translation supported? */
bool snoop_control; /* RO - is SNP filed supported? */ bool snoop_control; /* RO - is SNP filed supported? */
dma_addr_t root; /* Current root table pointer */ dma_addr_t root; /* Current root table pointer */