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https://github.com/Motorhead1991/qemu.git
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Model more parts of the ETRAX mmu (still alot missing).
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4056 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
edgar_igl
parent
e62b5b133b
commit
786c02f1ac
6 changed files with 202 additions and 52 deletions
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@ -30,6 +30,7 @@
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#include "mmu.h"
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#include "exec-all.h"
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#define D(x)
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static int cris_mmu_enabled(uint32_t rw_gc_cfg)
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{
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@ -60,7 +61,22 @@ static uint32_t cris_mmu_translate_seg(CPUState *env, int seg)
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}
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/* Used by the tlb decoder. */
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#define EXTRACT_FIELD(src, start, end) \
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(((src) >> start) & ((1 << (end - start + 1)) - 1))
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(((src) >> start) & ((1 << (end - start + 1)) - 1))
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static inline void set_field(uint32_t *dst, unsigned int val,
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unsigned int offset, unsigned int width)
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{
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uint32_t mask;
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mask = (1 << width) - 1;
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mask <<= offset;
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val <<= offset;
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val &= mask;
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D(printf ("val=%x mask=%x dst=%x\n", val, mask, *dst));
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*dst &= ~(mask);
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*dst |= val;
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}
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static int cris_mmu_translate_page(struct cris_mmu_result_t *res,
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CPUState *env, uint32_t vaddr,
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@ -69,46 +85,149 @@ static int cris_mmu_translate_page(struct cris_mmu_result_t *res,
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unsigned int vpage;
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unsigned int idx;
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uint32_t lo, hi;
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uint32_t vpn, pfn = 0, pid, fg, fv, fk, fw, fx;
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uint32_t tlb_vpn, tlb_pfn = 0;
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int tlb_pid, tlb_g, tlb_v, tlb_k, tlb_w, tlb_x;
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int cfg_v, cfg_k, cfg_w, cfg_x;
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int i, match = 0;
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uint32_t r_cause;
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uint32_t r_cfg;
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int rwcause;
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int update_sel = 0;
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r_cause = env->sregs[SFR_R_MM_CAUSE];
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r_cfg = env->sregs[SFR_RW_MM_CFG];
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rwcause = rw ? CRIS_MMU_ERR_WRITE : CRIS_MMU_ERR_READ;
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vpage = vaddr >> 13;
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idx = vpage & 31;
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vpage >>= 4;
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idx = vpage & 15;
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/* We know the index which to check on each set.
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Scan both I and D. */
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#if 0
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for (i = 0; i < 4; i++) {
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int j;
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for (j = 0; j < 16; j++) {
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lo = env->tlbsets[1][i][j].lo;
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hi = env->tlbsets[1][i][j].hi;
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tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
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tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
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printf ("TLB: [%d][%d] hi=%x lo=%x v=%x p=%x\n",
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i, j, hi, lo, tlb_vpn, tlb_pfn);
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}
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}
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#endif
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for (i = 0; i < 4; i++)
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{
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lo = env->tlbsets[0][i][idx].lo;
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hi = env->tlbsets[0][i][idx].hi;
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lo = env->tlbsets[1][i][idx].lo;
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hi = env->tlbsets[1][i][idx].hi;
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vpn = EXTRACT_FIELD(hi, 13, 31);
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pid = EXTRACT_FIELD(hi, 0, 7);
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tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
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tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
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if (vpn == vpage
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&& pid == env->pregs[PR_PID]) {
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D(printf ("TLB[%d][%d] tlbv=%x vpage=%x -> pfn=%x\n",
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i, idx, tlb_vpn, vpage, tlb_pfn));
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if (tlb_vpn == vpage) {
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match = 1;
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break;
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}
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}
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if (match) {
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pfn = EXTRACT_FIELD(lo, 13, 31);
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fg = EXTRACT_FIELD(lo, 4, 4);
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fv = EXTRACT_FIELD(lo, 3, 3);
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fk = EXTRACT_FIELD(lo, 2, 2);
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fw = EXTRACT_FIELD(lo, 1, 1);
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fx = EXTRACT_FIELD(lo, 0, 0);
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cfg_w = EXTRACT_FIELD(r_cfg, 19, 19);
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cfg_k = EXTRACT_FIELD(r_cfg, 18, 18);
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cfg_x = EXTRACT_FIELD(r_cfg, 17, 17);
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cfg_v = EXTRACT_FIELD(r_cfg, 16, 16);
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tlb_pid = EXTRACT_FIELD(hi, 0, 7);
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tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
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tlb_g = EXTRACT_FIELD(lo, 4, 4);
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tlb_v = EXTRACT_FIELD(lo, 3, 3);
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tlb_k = EXTRACT_FIELD(lo, 2, 2);
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tlb_w = EXTRACT_FIELD(lo, 1, 1);
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tlb_x = EXTRACT_FIELD(lo, 0, 0);
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/*
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set_exception_vector(0x04, i_mmu_refill);
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set_exception_vector(0x05, i_mmu_invalid);
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set_exception_vector(0x06, i_mmu_access);
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set_exception_vector(0x07, i_mmu_execute);
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set_exception_vector(0x08, d_mmu_refill);
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set_exception_vector(0x09, d_mmu_invalid);
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set_exception_vector(0x0a, d_mmu_access);
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set_exception_vector(0x0b, d_mmu_write);
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*/
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if (cfg_v && !tlb_v) {
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printf ("tlb: invalid\n");
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set_field(&r_cause, rwcause, 8, 9);
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match = 0;
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res->bf_vec = 0x9;
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update_sel = 1;
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}
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else if (!tlb_g
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&& tlb_pid != 0xff
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&& tlb_pid != env->pregs[PR_PID]
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&& cfg_w && !tlb_w) {
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printf ("tlb: wrong pid\n");
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match = 0;
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res->bf_vec = 0xa;
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}
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else if (rw && cfg_w && !tlb_w) {
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printf ("tlb: write protected\n");
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match = 0;
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res->bf_vec = 0xb;
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}
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} else
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update_sel = 1;
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if (update_sel) {
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/* miss. */
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env->sregs[SFR_RW_MM_TLB_SEL] = 0;
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D(printf ("tlb: miss %x vp=%x\n",
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env->sregs[SFR_RW_MM_TLB_SEL], vpage & 15));
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set_field(&env->sregs[SFR_RW_MM_TLB_SEL], vpage & 15, 0, 4);
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set_field(&env->sregs[SFR_RW_MM_TLB_SEL], 0, 4, 5);
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res->bf_vec = 0x8;
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}
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printf ("%s match=%d vaddr=%x vpage=%x vpn=%x pfn=%x pid=%x %x\n",
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__func__, match,
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vaddr, vpage,
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vpn, pfn, pid, env->pregs[PR_PID]);
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res->pfn = pfn;
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if (!match) {
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set_field(&r_cause, rwcause, 8, 9);
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set_field(&r_cause, vpage, 13, 19);
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set_field(&r_cause, env->pregs[PR_PID], 0, 8);
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env->sregs[SFR_R_MM_CAUSE] = r_cause;
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}
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D(printf ("%s mtch=%d pc=%x va=%x vpn=%x tlbvpn=%x pfn=%x pid=%x"
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" %x cause=%x sel=%x r13=%x\n",
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__func__, match, env->pc,
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vaddr, vpage,
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tlb_vpn, tlb_pfn, tlb_pid,
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env->pregs[PR_PID],
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r_cause,
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env->sregs[SFR_RW_MM_TLB_SEL],
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env->regs[13]));
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res->pfn = tlb_pfn;
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return !match;
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}
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/* Give us the vaddr corresponding to the latest TLB update. */
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target_ulong cris_mmu_tlb_latest_update(CPUState *env, uint32_t new_lo)
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{
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uint32_t sel = env->sregs[SFR_RW_MM_TLB_SEL];
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uint32_t vaddr;
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uint32_t hi;
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int set;
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int idx;
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idx = EXTRACT_FIELD(sel, 0, 4);
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set = EXTRACT_FIELD(sel, 4, 5);
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hi = env->tlbsets[1][set][idx].hi;
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vaddr = EXTRACT_FIELD(hi, 13, 31);
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return vaddr << TARGET_PAGE_BITS;
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}
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int cris_mmu_translate(struct cris_mmu_result_t *res,
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CPUState *env, uint32_t vaddr,
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int rw, int mmu_idx)
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@ -116,7 +235,7 @@ int cris_mmu_translate(struct cris_mmu_result_t *res,
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uint32_t phy = vaddr;
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int seg;
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int miss = 0;
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int is_user = mmu_idx == MMU_USER_IDX;
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int is_user = mmu_idx == MMU_USER_IDX;
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if (!cris_mmu_enabled(env->sregs[SFR_RW_GC_CFG])) {
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res->phy = vaddr;
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@ -142,7 +261,7 @@ int cris_mmu_translate(struct cris_mmu_result_t *res,
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res->phy = phy;
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}
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}
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// printf ("miss=%d v=%x -> p=%x\n", miss, vaddr, phy);
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D(printf ("miss=%d v=%x -> p=%x\n", miss, vaddr, phy));
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return miss;
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}
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#endif
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