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https://github.com/Motorhead1991/qemu.git
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cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass
we cannot in principle make the TCG Operations field definitions conditional on CONFIG_TCG in code that is included by both common_ss and specific_ss modules. Therefore, what we can do safely to restrict the TCG fields to TCG-only builds, is to move all tcg cpu operations into a separate header file, which is only included by TCG, target-specific code. This leaves just a NULL pointer in the cpu.h for the non-TCG builds. This also tidies up the code in all targets a bit, having all TCG cpu operations neatly contained by a dedicated data struct. Signed-off-by: Claudio Fontana <cfontana@suse.de> Message-Id: <20210204163931.7358-16-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Claudio Fontana
Richard Henderson
parent
c73bdb35a9
commit
7827168471
36 changed files with 582 additions and 306 deletions
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@ -21,6 +21,7 @@
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#include "qemu-common.h"
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#include "qemu/qemu-print.h"
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#include "cpu.h"
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#include "hw/core/tcg-cpu-ops.h"
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#include "trace.h"
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#include "disas/disas.h"
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#include "exec/exec-all.h"
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@ -213,8 +214,8 @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit)
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TARGET_FMT_lx "] %s\n",
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last_tb->tc.ptr, last_tb->pc,
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lookup_symbol(last_tb->pc));
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if (cc->tcg_ops.synchronize_from_tb) {
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cc->tcg_ops.synchronize_from_tb(cpu, last_tb);
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if (cc->tcg_ops->synchronize_from_tb) {
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cc->tcg_ops->synchronize_from_tb(cpu, last_tb);
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} else {
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assert(cc->set_pc);
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cc->set_pc(cpu, last_tb->pc);
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@ -262,8 +263,8 @@ static void cpu_exec_enter(CPUState *cpu)
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{
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CPUClass *cc = CPU_GET_CLASS(cpu);
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if (cc->tcg_ops.cpu_exec_enter) {
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cc->tcg_ops.cpu_exec_enter(cpu);
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if (cc->tcg_ops->cpu_exec_enter) {
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cc->tcg_ops->cpu_exec_enter(cpu);
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}
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}
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@ -271,8 +272,8 @@ static void cpu_exec_exit(CPUState *cpu)
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{
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CPUClass *cc = CPU_GET_CLASS(cpu);
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if (cc->tcg_ops.cpu_exec_exit) {
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cc->tcg_ops.cpu_exec_exit(cpu);
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if (cc->tcg_ops->cpu_exec_exit) {
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cc->tcg_ops->cpu_exec_exit(cpu);
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}
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}
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@ -512,8 +513,8 @@ static inline void cpu_handle_debug_exception(CPUState *cpu)
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}
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}
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if (cc->tcg_ops.debug_excp_handler) {
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cc->tcg_ops.debug_excp_handler(cpu);
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if (cc->tcg_ops->debug_excp_handler) {
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cc->tcg_ops->debug_excp_handler(cpu);
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}
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}
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@ -547,7 +548,7 @@ static inline bool cpu_handle_exception(CPUState *cpu, int *ret)
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loop */
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#if defined(TARGET_I386)
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CPUClass *cc = CPU_GET_CLASS(cpu);
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cc->tcg_ops.do_interrupt(cpu);
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cc->tcg_ops->do_interrupt(cpu);
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#endif
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*ret = cpu->exception_index;
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cpu->exception_index = -1;
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@ -556,7 +557,7 @@ static inline bool cpu_handle_exception(CPUState *cpu, int *ret)
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if (replay_exception()) {
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CPUClass *cc = CPU_GET_CLASS(cpu);
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qemu_mutex_lock_iothread();
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cc->tcg_ops.do_interrupt(cpu);
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cc->tcg_ops->do_interrupt(cpu);
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qemu_mutex_unlock_iothread();
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cpu->exception_index = -1;
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@ -655,8 +656,8 @@ static inline bool cpu_handle_interrupt(CPUState *cpu,
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True when it is, and we should restart on a new TB,
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and via longjmp via cpu_loop_exit. */
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else {
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if (cc->tcg_ops.cpu_exec_interrupt &&
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cc->tcg_ops.cpu_exec_interrupt(cpu, interrupt_request)) {
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if (cc->tcg_ops->cpu_exec_interrupt &&
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cc->tcg_ops->cpu_exec_interrupt(cpu, interrupt_request)) {
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if (need_replay_interrupt(interrupt_request)) {
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replay_interrupt();
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}
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@ -834,7 +835,7 @@ void tcg_exec_realizefn(CPUState *cpu, Error **errp)
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CPUClass *cc = CPU_GET_CLASS(cpu);
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if (!tcg_target_initialized) {
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cc->tcg_ops.initialize();
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cc->tcg_ops->initialize();
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tcg_target_initialized = true;
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}
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tlb_init(cpu);
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@ -20,6 +20,7 @@
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#include "qemu/osdep.h"
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#include "qemu/main-loop.h"
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#include "cpu.h"
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#include "hw/core/tcg-cpu-ops.h"
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#include "exec/exec-all.h"
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#include "exec/memory.h"
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#include "exec/address-spaces.h"
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@ -1305,11 +1306,37 @@ static void tlb_fill(CPUState *cpu, target_ulong addr, int size,
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* This is not a probe, so only valid return is success; failure
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* should result in exception + longjmp to the cpu loop.
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*/
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ok = cc->tcg_ops.tlb_fill(cpu, addr, size,
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access_type, mmu_idx, false, retaddr);
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ok = cc->tcg_ops->tlb_fill(cpu, addr, size,
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access_type, mmu_idx, false, retaddr);
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assert(ok);
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}
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static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr,
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MMUAccessType access_type,
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int mmu_idx, uintptr_t retaddr)
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{
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CPUClass *cc = CPU_GET_CLASS(cpu);
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cc->tcg_ops->do_unaligned_access(cpu, addr, access_type, mmu_idx, retaddr);
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}
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static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr,
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vaddr addr, unsigned size,
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MMUAccessType access_type,
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int mmu_idx, MemTxAttrs attrs,
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MemTxResult response,
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uintptr_t retaddr)
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{
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CPUClass *cc = CPU_GET_CLASS(cpu);
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if (!cpu->ignore_memory_transaction_failures &&
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cc->tcg_ops->do_transaction_failed) {
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cc->tcg_ops->do_transaction_failed(cpu, physaddr, addr, size,
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access_type, mmu_idx, attrs,
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response, retaddr);
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}
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}
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static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
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int mmu_idx, target_ulong addr, uintptr_t retaddr,
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MMUAccessType access_type, MemOp op)
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@ -1577,8 +1604,8 @@ static int probe_access_internal(CPUArchState *env, target_ulong addr,
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CPUState *cs = env_cpu(env);
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CPUClass *cc = CPU_GET_CLASS(cs);
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if (!cc->tcg_ops.tlb_fill(cs, addr, fault_size, access_type,
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mmu_idx, nonfault, retaddr)) {
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if (!cc->tcg_ops->tlb_fill(cs, addr, fault_size, access_type,
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mmu_idx, nonfault, retaddr)) {
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/* Non-faulting page table read failed. */
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*phost = NULL;
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return TLB_INVALID_MASK;
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@ -18,6 +18,7 @@
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "hw/core/tcg-cpu-ops.h"
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#include "disas/disas.h"
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#include "exec/exec-all.h"
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#include "tcg/tcg.h"
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@ -187,8 +188,8 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info,
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clear_helper_retaddr();
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cc = CPU_GET_CLASS(cpu);
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cc->tcg_ops.tlb_fill(cpu, address, 0, access_type,
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MMU_USER_IDX, false, pc);
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cc->tcg_ops->tlb_fill(cpu, address, 0, access_type,
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MMU_USER_IDX, false, pc);
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g_assert_not_reached();
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}
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@ -218,8 +219,8 @@ static int probe_access_internal(CPUArchState *env, target_ulong addr,
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} else {
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CPUState *cpu = env_cpu(env);
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CPUClass *cc = CPU_GET_CLASS(cpu);
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cc->tcg_ops.tlb_fill(cpu, addr, fault_size, access_type,
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MMU_USER_IDX, false, ra);
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cc->tcg_ops->tlb_fill(cpu, addr, fault_size, access_type,
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MMU_USER_IDX, false, ra);
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g_assert_not_reached();
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}
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}
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