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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4440 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
blueswir1
parent
8686c490f7
commit
77f193daa8
13 changed files with 395 additions and 200 deletions
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@ -347,7 +347,7 @@ void cpu_set_cwp(CPUSPARCState *env1, int new_cwp);
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#ifdef TARGET_SPARC64
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#define GET_CCR(env) (((env->xcc >> 20) << 4) | ((env->psr & PSR_ICC) >> 20))
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#define PUT_CCR(env, val) do { int _tmp = val; \
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env->xcc = (_tmp >> 4) << 20; \
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env->xcc = (_tmp >> 4) << 20; \
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env->psr = (_tmp & 0xf) << 20; \
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} while (0)
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#define GET_CWP64(env) (NWINDOWS - 1 - (env)->cwp)
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@ -193,7 +193,8 @@ static int get_physical_address(CPUState *env, target_phys_addr_t *physical,
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return (3 << 8) | (4 << 2);
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case 2: /* L3 PTE */
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virt_addr = address & TARGET_PAGE_MASK;
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page_offset = (address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1);
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page_offset = (address & TARGET_PAGE_MASK) &
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(TARGET_PAGE_SIZE - 1);
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}
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break;
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case 2: /* L2 PTE */
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@ -243,7 +244,8 @@ int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
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target_ulong vaddr;
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int error_code = 0, prot, ret = 0, access_index;
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error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, mmu_idx);
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error_code = get_physical_address(env, &paddr, &prot, &access_index,
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address, rw, mmu_idx);
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if (error_code == 0) {
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vaddr = address & TARGET_PAGE_MASK;
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paddr &= TARGET_PAGE_MASK;
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@ -387,7 +389,8 @@ void dump_mmu(CPUState *env)
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/*
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* UltraSparc IIi I/DMMUs
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*/
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static int get_physical_address_data(CPUState *env, target_phys_addr_t *physical, int *prot,
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static int get_physical_address_data(CPUState *env,
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target_phys_addr_t *physical, int *prot,
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target_ulong address, int rw, int is_user)
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{
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target_ulong mask;
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@ -423,7 +426,8 @@ static int get_physical_address_data(CPUState *env, target_phys_addr_t *physical
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((env->dtlb_tte[i] & 0x4) && is_user) ||
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(!(env->dtlb_tte[i] & 0x2) && (rw == 1))) {
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if (env->dmmuregs[3]) /* Fault status register */
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env->dmmuregs[3] = 2; /* overflow (not read before another fault) */
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env->dmmuregs[3] = 2; /* overflow (not read before
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another fault) */
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env->dmmuregs[3] |= (is_user << 3) | ((rw == 1) << 2) | 1;
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env->dmmuregs[4] = address; /* Fault address register */
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env->exception_index = TT_DFAULT;
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@ -432,7 +436,8 @@ static int get_physical_address_data(CPUState *env, target_phys_addr_t *physical
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#endif
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return 1;
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}
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*physical = (env->dtlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL);
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*physical = (env->dtlb_tte[i] & mask & 0x1fffffff000ULL) +
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(address & ~mask & 0x1fffffff000ULL);
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*prot = PAGE_READ;
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if (env->dtlb_tte[i] & 0x2)
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*prot |= PAGE_WRITE;
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@ -446,7 +451,8 @@ static int get_physical_address_data(CPUState *env, target_phys_addr_t *physical
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return 1;
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}
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static int get_physical_address_code(CPUState *env, target_phys_addr_t *physical, int *prot,
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static int get_physical_address_code(CPUState *env,
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target_phys_addr_t *physical, int *prot,
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target_ulong address, int is_user)
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{
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target_ulong mask;
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@ -481,7 +487,8 @@ static int get_physical_address_code(CPUState *env, target_phys_addr_t *physical
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if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0 ||
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((env->itlb_tte[i] & 0x4) && is_user)) {
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if (env->immuregs[3]) /* Fault status register */
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env->immuregs[3] = 2; /* overflow (not read before another fault) */
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env->immuregs[3] = 2; /* overflow (not read before
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another fault) */
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env->immuregs[3] |= (is_user << 3) | 1;
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env->exception_index = TT_TFAULT;
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#ifdef DEBUG_MMU
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@ -489,7 +496,8 @@ static int get_physical_address_code(CPUState *env, target_phys_addr_t *physical
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#endif
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return 1;
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}
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*physical = (env->itlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL);
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*physical = (env->itlb_tte[i] & mask & 0x1fffffff000ULL) +
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(address & ~mask & 0x1fffffff000ULL);
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*prot = PAGE_EXEC;
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return 0;
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}
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@ -523,12 +531,15 @@ int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
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target_phys_addr_t paddr;
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int error_code = 0, prot, ret = 0, access_index;
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error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, mmu_idx);
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error_code = get_physical_address(env, &paddr, &prot, &access_index,
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address, rw, mmu_idx);
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if (error_code == 0) {
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virt_addr = address & TARGET_PAGE_MASK;
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vaddr = virt_addr + ((address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1));
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vaddr = virt_addr + ((address & TARGET_PAGE_MASK) &
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(TARGET_PAGE_SIZE - 1));
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#ifdef DEBUG_MMU
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printf("Translate at 0x%" PRIx64 " -> 0x%" PRIx64 ", vaddr 0x%" PRIx64 "\n", address, paddr, vaddr);
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printf("Translate at 0x%" PRIx64 " -> 0x%" PRIx64 ", vaddr 0x%" PRIx64
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"\n", address, paddr, vaddr);
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#endif
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ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
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return ret;
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@ -543,7 +554,8 @@ void dump_mmu(CPUState *env)
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unsigned int i;
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const char *mask;
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printf("MMU contexts: Primary: %" PRId64 ", Secondary: %" PRId64 "\n", env->dmmuregs[1], env->dmmuregs[2]);
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printf("MMU contexts: Primary: %" PRId64 ", Secondary: %" PRId64 "\n",
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env->dmmuregs[1], env->dmmuregs[2]);
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if ((env->lsu & DMMU_E) == 0) {
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printf("DMMU disabled\n");
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} else {
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@ -565,7 +577,8 @@ void dump_mmu(CPUState *env)
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break;
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}
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if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) {
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printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, %s, ctx %" PRId64 "\n",
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printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx
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", %s, %s, %s, %s, ctx %" PRId64 "\n",
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env->dtlb_tag[i] & ~0x1fffULL,
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env->dtlb_tte[i] & 0x1ffffffe000ULL,
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mask,
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@ -597,7 +610,8 @@ void dump_mmu(CPUState *env)
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break;
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}
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if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) {
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printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, ctx %" PRId64 "\n",
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printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx
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", %s, %s, %s, ctx %" PRId64 "\n",
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env->itlb_tag[i] & ~0x1fffULL,
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env->itlb_tte[i] & 0x1ffffffe000ULL,
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mask,
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@ -1206,7 +1220,8 @@ static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model)
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goto error;
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}
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} else {
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fprintf(stderr, "feature string `%s' not in format (+feature|-feature|feature=xyz)\n", featurestr);
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fprintf(stderr, "feature string `%s' not in format "
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"(+feature|-feature|feature=xyz)\n", featurestr);
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goto error;
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}
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featurestr = strtok(NULL, ",");
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@ -1224,7 +1239,7 @@ static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model)
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return -1;
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}
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void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
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void sparc_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
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{
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unsigned int i;
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@ -1234,14 +1249,17 @@ void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
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sparc_defs[i].iu_version,
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sparc_defs[i].fpu_version,
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sparc_defs[i].mmu_version);
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print_features(f, cpu_fprintf, CPU_DEFAULT_FEATURES & ~sparc_defs[i].features, "-");
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print_features(f, cpu_fprintf, ~CPU_DEFAULT_FEATURES & sparc_defs[i].features, "+");
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print_features(f, cpu_fprintf, CPU_DEFAULT_FEATURES &
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~sparc_defs[i].features, "-");
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print_features(f, cpu_fprintf, ~CPU_DEFAULT_FEATURES &
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sparc_defs[i].features, "+");
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(*cpu_fprintf)(f, "\n");
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}
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(*cpu_fprintf)(f, "CPU feature flags (+/-): ");
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print_features(f, cpu_fprintf, -1, NULL);
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(*cpu_fprintf)(f, "\n");
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(*cpu_fprintf)(f, "Numerical features (=): iu_version fpu_version mmu_version\n");
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(*cpu_fprintf)(f, "Numerical features (=): iu_version fpu_version "
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"mmu_version\n");
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}
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#define GET_FLAG(a,b) ((env->psr & a)?b:'-')
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@ -1252,7 +1270,8 @@ void cpu_dump_state(CPUState *env, FILE *f,
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{
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int i, x;
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cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, env->npc);
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cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc,
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env->npc);
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cpu_fprintf(f, "General Registers:\n");
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for (i = 0; i < 4; i++)
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cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
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@ -1283,15 +1302,16 @@ void cpu_dump_state(CPUState *env, FILE *f,
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#ifdef TARGET_SPARC64
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cpu_fprintf(f, "pstate: 0x%08x ccr: 0x%02x asi: 0x%02x tl: %d fprs: %d\n",
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env->pstate, GET_CCR(env), env->asi, env->tl, env->fprs);
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cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate %d cleanwin %d cwp %d\n",
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cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate %d "
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"cleanwin %d cwp %d\n",
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env->cansave, env->canrestore, env->otherwin, env->wstate,
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env->cleanwin, NWINDOWS - 1 - env->cwp);
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#else
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cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n", GET_PSR(env),
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GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'),
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GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'),
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env->psrs?'S':'-', env->psrps?'P':'-',
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env->psret?'E':'-', env->wim);
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cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n",
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GET_PSR(env), GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'),
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GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'),
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env->psrs?'S':'-', env->psrps?'P':'-',
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env->psret?'E':'-', env->wim);
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#endif
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cpu_fprintf(f, "fsr: 0x%08x\n", GET_FSR32(env));
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}
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@ -795,15 +795,19 @@ GEN_FCMP(fcmped_fcc3, float64, DT0, DT1, 26, 1);
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GEN_FCMP(fcmpeq_fcc3, float128, QT0, QT1, 26, 1);
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#endif
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#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && defined(DEBUG_MXCC)
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#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \
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defined(DEBUG_MXCC)
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static void dump_mxcc(CPUState *env)
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{
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printf("mxccdata: %016llx %016llx %016llx %016llx\n",
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env->mxccdata[0], env->mxccdata[1], env->mxccdata[2], env->mxccdata[3]);
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env->mxccdata[0], env->mxccdata[1],
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env->mxccdata[2], env->mxccdata[3]);
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printf("mxccregs: %016llx %016llx %016llx %016llx\n"
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" %016llx %016llx %016llx %016llx\n",
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env->mxccregs[0], env->mxccregs[1], env->mxccregs[2], env->mxccregs[3],
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env->mxccregs[4], env->mxccregs[5], env->mxccregs[6], env->mxccregs[7]);
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env->mxccregs[0], env->mxccregs[1],
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env->mxccregs[2], env->mxccregs[3],
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env->mxccregs[4], env->mxccregs[5],
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env->mxccregs[6], env->mxccregs[7]);
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}
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#endif
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@ -851,32 +855,38 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
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if (size == 8)
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ret = env->mxccregs[3];
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else
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DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
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DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
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size);
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break;
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case 0x01c00a04: /* MXCC control register */
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if (size == 4)
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ret = env->mxccregs[3];
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else
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DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
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DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
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size);
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break;
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case 0x01c00c00: /* Module reset register */
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if (size == 8) {
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ret = env->mxccregs[5];
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// should we do something here?
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} else
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DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
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DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
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size);
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break;
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case 0x01c00f00: /* MBus port address register */
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if (size == 8)
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ret = env->mxccregs[7];
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else
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DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
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DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
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size);
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break;
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default:
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DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr, size);
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DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr,
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size);
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break;
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}
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DPRINTF_MXCC("asi = %d, size = %d, sign = %d, addr = %08x -> ret = %08x,"
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DPRINTF_MXCC("asi = %d, size = %d, sign = %d, "
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"addr = %08x -> ret = %08x,"
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"addr = %08x\n", asi, size, sign, last_addr, ret, addr);
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#ifdef DEBUG_MXCC
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dump_mxcc(env);
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@ -1050,76 +1060,97 @@ void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size)
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if (size == 8)
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env->mxccdata[0] = val;
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else
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DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
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DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
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size);
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break;
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case 0x01c00008: /* MXCC stream data register 1 */
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if (size == 8)
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env->mxccdata[1] = val;
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else
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DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
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DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
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size);
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break;
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case 0x01c00010: /* MXCC stream data register 2 */
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if (size == 8)
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env->mxccdata[2] = val;
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else
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DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
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DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
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size);
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break;
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case 0x01c00018: /* MXCC stream data register 3 */
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if (size == 8)
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env->mxccdata[3] = val;
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else
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DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
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DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
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size);
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break;
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case 0x01c00100: /* MXCC stream source */
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if (size == 8)
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env->mxccregs[0] = val;
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else
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DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
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env->mxccdata[0] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 0);
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env->mxccdata[1] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 8);
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env->mxccdata[2] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 16);
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env->mxccdata[3] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 24);
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DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
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size);
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env->mxccdata[0] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
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0);
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env->mxccdata[1] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
|
||||
8);
|
||||
env->mxccdata[2] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
|
||||
16);
|
||||
env->mxccdata[3] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
|
||||
24);
|
||||
break;
|
||||
case 0x01c00200: /* MXCC stream destination */
|
||||
if (size == 8)
|
||||
env->mxccregs[1] = val;
|
||||
else
|
||||
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
|
||||
stq_phys((env->mxccregs[1] & 0xffffffffULL) + 0, env->mxccdata[0]);
|
||||
stq_phys((env->mxccregs[1] & 0xffffffffULL) + 8, env->mxccdata[1]);
|
||||
stq_phys((env->mxccregs[1] & 0xffffffffULL) + 16, env->mxccdata[2]);
|
||||
stq_phys((env->mxccregs[1] & 0xffffffffULL) + 24, env->mxccdata[3]);
|
||||
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
||||
size);
|
||||
stq_phys((env->mxccregs[1] & 0xffffffffULL) + 0,
|
||||
env->mxccdata[0]);
|
||||
stq_phys((env->mxccregs[1] & 0xffffffffULL) + 8,
|
||||
env->mxccdata[1]);
|
||||
stq_phys((env->mxccregs[1] & 0xffffffffULL) + 16,
|
||||
env->mxccdata[2]);
|
||||
stq_phys((env->mxccregs[1] & 0xffffffffULL) + 24,
|
||||
env->mxccdata[3]);
|
||||
break;
|
||||
case 0x01c00a00: /* MXCC control register */
|
||||
if (size == 8)
|
||||
env->mxccregs[3] = val;
|
||||
else
|
||||
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
|
||||
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
||||
size);
|
||||
break;
|
||||
case 0x01c00a04: /* MXCC control register */
|
||||
if (size == 4)
|
||||
env->mxccregs[3] = (env->mxccregs[0xa] & 0xffffffff00000000ULL) | val;
|
||||
env->mxccregs[3] = (env->mxccregs[0xa] & 0xffffffff00000000ULL)
|
||||
| val;
|
||||
else
|
||||
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
|
||||
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
||||
size);
|
||||
break;
|
||||
case 0x01c00e00: /* MXCC error register */
|
||||
// writing a 1 bit clears the error
|
||||
if (size == 8)
|
||||
env->mxccregs[6] &= ~val;
|
||||
else
|
||||
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
|
||||
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
||||
size);
|
||||
break;
|
||||
case 0x01c00f00: /* MBus port address register */
|
||||
if (size == 8)
|
||||
env->mxccregs[7] = val;
|
||||
else
|
||||
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
|
||||
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
||||
size);
|
||||
break;
|
||||
default:
|
||||
DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr, size);
|
||||
DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr,
|
||||
size);
|
||||
break;
|
||||
}
|
||||
DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %08x\n", asi, size, addr, val);
|
||||
DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %08x\n", asi,
|
||||
size, addr, val);
|
||||
#ifdef DEBUG_MXCC
|
||||
dump_mxcc(env);
|
||||
#endif
|
||||
|
|
@ -1192,7 +1223,8 @@ void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size)
|
|||
break;
|
||||
}
|
||||
if (oldreg != env->mmuregs[reg]) {
|
||||
DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n", reg, oldreg, env->mmuregs[reg]);
|
||||
DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n",
|
||||
reg, oldreg, env->mmuregs[reg]);
|
||||
}
|
||||
#ifdef DEBUG_MMU
|
||||
dump_mmu(env);
|
||||
|
|
@ -1317,7 +1349,8 @@ void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size)
|
|||
case 0x30: // store buffer tags or Turbosparc secondary cache diagnostic
|
||||
case 0x31: // store buffer data, Ross RT620 I-cache flush or
|
||||
// Turbosparc snoop RAM
|
||||
case 0x32: // store buffer control or Turbosparc page table descriptor diagnostic
|
||||
case 0x32: // store buffer control or Turbosparc page table
|
||||
// descriptor diagnostic
|
||||
case 0x36: /* I-cache flash clear */
|
||||
case 0x37: /* D-cache flash clear */
|
||||
case 0x38: /* breakpoint diagnostics */
|
||||
|
|
@ -1860,7 +1893,8 @@ void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
|
|||
// Mappings generated during D/I MMU disabled mode are
|
||||
// invalid in normal mode
|
||||
if (oldreg != env->lsu) {
|
||||
DPRINTF_MMU("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n", oldreg, env->lsu);
|
||||
DPRINTF_MMU("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n",
|
||||
oldreg, env->lsu);
|
||||
#ifdef DEBUG_MMU
|
||||
dump_mmu(env);
|
||||
#endif
|
||||
|
|
@ -1894,7 +1928,8 @@ void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
|
|||
}
|
||||
env->immuregs[reg] = val;
|
||||
if (oldreg != env->immuregs[reg]) {
|
||||
DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
|
||||
DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08"
|
||||
PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
|
||||
}
|
||||
#ifdef DEBUG_MMU
|
||||
dump_mmu(env);
|
||||
|
|
@ -1963,7 +1998,8 @@ void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
|
|||
}
|
||||
env->dmmuregs[reg] = val;
|
||||
if (oldreg != env->dmmuregs[reg]) {
|
||||
DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
|
||||
DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08"
|
||||
PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
|
||||
}
|
||||
#ifdef DEBUG_MMU
|
||||
dump_mmu(env);
|
||||
|
|
@ -2042,7 +2078,8 @@ void helper_ldf_asi(target_ulong addr, int asi, int size, int rd)
|
|||
}
|
||||
helper_check_align(addr, 0x3f);
|
||||
for (i = 0; i < 16; i++) {
|
||||
*(uint32_t *)&env->fpr[rd++] = helper_ld_asi(addr, asi & 0x8f, 4, 0);
|
||||
*(uint32_t *)&env->fpr[rd++] = helper_ld_asi(addr, asi & 0x8f, 4,
|
||||
0);
|
||||
addr += 4;
|
||||
}
|
||||
|
||||
|
|
@ -2697,7 +2734,8 @@ void do_interrupt(int intno)
|
|||
#endif
|
||||
#if !defined(CONFIG_USER_ONLY)
|
||||
if (env->tl == MAXTL) {
|
||||
cpu_abort(env, "Trap 0x%04x while trap level is MAXTL, Error state", env->exception_index);
|
||||
cpu_abort(env, "Trap 0x%04x while trap level is MAXTL, Error state",
|
||||
env->exception_index);
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
|
@ -2807,7 +2845,8 @@ void do_interrupt(int intno)
|
|||
#endif
|
||||
#if !defined(CONFIG_USER_ONLY)
|
||||
if (env->psret == 0) {
|
||||
cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state", env->exception_index);
|
||||
cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state",
|
||||
env->exception_index);
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
|
@ -2833,7 +2872,8 @@ static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
|
|||
#define MMUSUFFIX _mmu
|
||||
#define ALIGNED_ONLY
|
||||
#ifdef __s390__
|
||||
# define GETPC() ((void*)((unsigned long)__builtin_return_address(0) & 0x7fffffffUL))
|
||||
# define GETPC() ((void*)((unsigned long)__builtin_return_address(0) & \
|
||||
0x7fffffffUL))
|
||||
#else
|
||||
# define GETPC() (__builtin_return_address(0))
|
||||
#endif
|
||||
|
|
@ -2915,8 +2955,8 @@ void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
|
|||
env = cpu_single_env;
|
||||
#ifdef DEBUG_UNASSIGNED
|
||||
if (is_asi)
|
||||
printf("Unassigned mem %s access to " TARGET_FMT_plx " asi 0x%02x from "
|
||||
TARGET_FMT_lx "\n",
|
||||
printf("Unassigned mem %s access to " TARGET_FMT_plx
|
||||
" asi 0x%02x from " TARGET_FMT_lx "\n",
|
||||
is_exec ? "exec" : is_write ? "write" : "read", addr, is_asi,
|
||||
env->pc);
|
||||
else
|
||||
|
|
@ -2955,8 +2995,8 @@ void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
|
|||
generated code */
|
||||
saved_env = env;
|
||||
env = cpu_single_env;
|
||||
printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx "\n",
|
||||
addr, env->pc);
|
||||
printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx
|
||||
"\n", addr, env->pc);
|
||||
env = saved_env;
|
||||
#endif
|
||||
if (is_exec)
|
||||
|
|
|
|||
|
|
@ -38,7 +38,8 @@
|
|||
according to jump_pc[T2] */
|
||||
|
||||
/* global register indexes */
|
||||
static TCGv cpu_env, cpu_T[2], cpu_regwptr, cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
|
||||
static TCGv cpu_env, cpu_T[2], cpu_regwptr;
|
||||
static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
|
||||
static TCGv cpu_psr, cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8];
|
||||
static TCGv cpu_cond, cpu_src1, cpu_src2, cpu_dst, cpu_addr, cpu_val;
|
||||
#ifdef TARGET_SPARC64
|
||||
|
|
@ -109,60 +110,78 @@ static void gen_op_store_FT0_fpr(unsigned int dst)
|
|||
static void gen_op_load_fpr_DT0(unsigned int src)
|
||||
{
|
||||
tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
|
||||
tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.upper));
|
||||
tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
|
||||
offsetof(CPU_DoubleU, l.upper));
|
||||
tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
|
||||
tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.lower));
|
||||
tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
|
||||
offsetof(CPU_DoubleU, l.lower));
|
||||
}
|
||||
|
||||
static void gen_op_load_fpr_DT1(unsigned int src)
|
||||
{
|
||||
tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
|
||||
tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) + offsetof(CPU_DoubleU, l.upper));
|
||||
tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) +
|
||||
offsetof(CPU_DoubleU, l.upper));
|
||||
tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
|
||||
tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) + offsetof(CPU_DoubleU, l.lower));
|
||||
tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) +
|
||||
offsetof(CPU_DoubleU, l.lower));
|
||||
}
|
||||
|
||||
static void gen_op_store_DT0_fpr(unsigned int dst)
|
||||
{
|
||||
tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.upper));
|
||||
tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
|
||||
offsetof(CPU_DoubleU, l.upper));
|
||||
tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
|
||||
tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.lower));
|
||||
tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
|
||||
offsetof(CPU_DoubleU, l.lower));
|
||||
tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
|
||||
}
|
||||
|
||||
static void gen_op_load_fpr_QT0(unsigned int src)
|
||||
{
|
||||
tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
|
||||
tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upmost));
|
||||
tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
|
||||
offsetof(CPU_QuadU, l.upmost));
|
||||
tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
|
||||
tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upper));
|
||||
tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
|
||||
offsetof(CPU_QuadU, l.upper));
|
||||
tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
|
||||
tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lower));
|
||||
tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
|
||||
offsetof(CPU_QuadU, l.lower));
|
||||
tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
|
||||
tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lowest));
|
||||
tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
|
||||
offsetof(CPU_QuadU, l.lowest));
|
||||
}
|
||||
|
||||
static void gen_op_load_fpr_QT1(unsigned int src)
|
||||
{
|
||||
tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
|
||||
tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.upmost));
|
||||
tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
|
||||
offsetof(CPU_QuadU, l.upmost));
|
||||
tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
|
||||
tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.upper));
|
||||
tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
|
||||
offsetof(CPU_QuadU, l.upper));
|
||||
tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
|
||||
tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.lower));
|
||||
tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
|
||||
offsetof(CPU_QuadU, l.lower));
|
||||
tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
|
||||
tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.lowest));
|
||||
tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
|
||||
offsetof(CPU_QuadU, l.lowest));
|
||||
}
|
||||
|
||||
static void gen_op_store_QT0_fpr(unsigned int dst)
|
||||
{
|
||||
tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upmost));
|
||||
tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
|
||||
offsetof(CPU_QuadU, l.upmost));
|
||||
tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
|
||||
tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upper));
|
||||
tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
|
||||
offsetof(CPU_QuadU, l.upper));
|
||||
tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
|
||||
tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lower));
|
||||
tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
|
||||
offsetof(CPU_QuadU, l.lower));
|
||||
tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 2]));
|
||||
tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lowest));
|
||||
tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
|
||||
offsetof(CPU_QuadU, l.lowest));
|
||||
tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 3]));
|
||||
}
|
||||
|
||||
|
|
@ -1591,7 +1610,8 @@ static inline TCGv gen_get_asi(int insn, TCGv r_addr)
|
|||
return r_asi;
|
||||
}
|
||||
|
||||
static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size, int sign)
|
||||
static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
|
||||
int sign)
|
||||
{
|
||||
TCGv r_asi;
|
||||
|
||||
|
|
@ -1664,7 +1684,8 @@ static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
|
|||
tcg_const_i32(8));
|
||||
}
|
||||
|
||||
static inline void gen_cas_asi(TCGv dst, TCGv addr, TCGv val2, int insn, int rd)
|
||||
static inline void gen_cas_asi(TCGv dst, TCGv addr, TCGv val2, int insn,
|
||||
int rd)
|
||||
{
|
||||
TCGv r_val1, r_asi;
|
||||
|
||||
|
|
@ -1674,7 +1695,8 @@ static inline void gen_cas_asi(TCGv dst, TCGv addr, TCGv val2, int insn, int rd)
|
|||
tcg_gen_helper_1_4(helper_cas_asi, dst, addr, r_val1, val2, r_asi);
|
||||
}
|
||||
|
||||
static inline void gen_casx_asi(TCGv dst, TCGv addr, TCGv val2, int insn, int rd)
|
||||
static inline void gen_casx_asi(TCGv dst, TCGv addr, TCGv val2, int insn,
|
||||
int rd)
|
||||
{
|
||||
TCGv r_asi;
|
||||
|
||||
|
|
@ -1685,7 +1707,8 @@ static inline void gen_casx_asi(TCGv dst, TCGv addr, TCGv val2, int insn, int rd
|
|||
|
||||
#elif !defined(CONFIG_USER_ONLY)
|
||||
|
||||
static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size, int sign)
|
||||
static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
|
||||
int sign)
|
||||
{
|
||||
int asi;
|
||||
|
||||
|
|
@ -1970,7 +1993,8 @@ static void disas_sparc_insn(DisasContext * dc)
|
|||
SPARCv8 manual, rdy on the
|
||||
microSPARC II */
|
||||
#endif
|
||||
tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, y));
|
||||
tcg_gen_ld_tl(cpu_dst, cpu_env,
|
||||
offsetof(CPUSPARCState, y));
|
||||
gen_movl_TN_reg(rd, cpu_dst);
|
||||
break;
|
||||
#ifdef TARGET_SPARC64
|
||||
|
|
@ -1979,7 +2003,8 @@ static void disas_sparc_insn(DisasContext * dc)
|
|||
gen_movl_TN_reg(rd, cpu_dst);
|
||||
break;
|
||||
case 0x3: /* V9 rdasi */
|
||||
tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, asi));
|
||||
tcg_gen_ld_i32(cpu_tmp32, cpu_env,
|
||||
offsetof(CPUSPARCState, asi));
|
||||
tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
|
||||
gen_movl_TN_reg(rd, cpu_dst);
|
||||
break;
|
||||
|
|
@ -1999,7 +2024,8 @@ static void disas_sparc_insn(DisasContext * dc)
|
|||
gen_movl_TN_reg(rd, tcg_const_tl(dc->pc));
|
||||
break;
|
||||
case 0x6: /* V9 rdfprs */
|
||||
tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fprs));
|
||||
tcg_gen_ld_i32(cpu_tmp32, cpu_env,
|
||||
offsetof(CPUSPARCState, fprs));
|
||||
tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
|
||||
gen_movl_TN_reg(rd, cpu_dst);
|
||||
break;
|
||||
|
|
@ -2008,11 +2034,13 @@ static void disas_sparc_insn(DisasContext * dc)
|
|||
case 0x13: /* Graphics Status */
|
||||
if (gen_trap_ifnofpu(dc, cpu_cond))
|
||||
goto jmp_insn;
|
||||
tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, gsr));
|
||||
tcg_gen_ld_tl(cpu_dst, cpu_env,
|
||||
offsetof(CPUSPARCState, gsr));
|
||||
gen_movl_TN_reg(rd, cpu_dst);
|
||||
break;
|
||||
case 0x17: /* Tick compare */
|
||||
tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, tick_cmpr));
|
||||
tcg_gen_ld_tl(cpu_dst, cpu_env,
|
||||
offsetof(CPUSPARCState, tick_cmpr));
|
||||
gen_movl_TN_reg(rd, cpu_dst);
|
||||
break;
|
||||
case 0x18: /* System tick */
|
||||
|
|
@ -2028,7 +2056,8 @@ static void disas_sparc_insn(DisasContext * dc)
|
|||
}
|
||||
break;
|
||||
case 0x19: /* System tick compare */
|
||||
tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, stick_cmpr));
|
||||
tcg_gen_ld_tl(cpu_dst, cpu_env,
|
||||
offsetof(CPUSPARCState, stick_cmpr));
|
||||
gen_movl_TN_reg(rd, cpu_dst);
|
||||
break;
|
||||
case 0x10: /* Performance Control */
|
||||
|
|
@ -2059,20 +2088,24 @@ static void disas_sparc_insn(DisasContext * dc)
|
|||
// gen_op_rdhtstate();
|
||||
break;
|
||||
case 3: // hintp
|
||||
tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, hintp));
|
||||
tcg_gen_ld_i32(cpu_tmp32, cpu_env,
|
||||
offsetof(CPUSPARCState, hintp));
|
||||
tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
|
||||
break;
|
||||
case 5: // htba
|
||||
tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, htba));
|
||||
tcg_gen_ld_i32(cpu_tmp32, cpu_env,
|
||||
offsetof(CPUSPARCState, htba));
|
||||
tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
|
||||
break;
|
||||
case 6: // hver
|
||||
tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, hver));
|
||||
tcg_gen_ld_i32(cpu_tmp32, cpu_env,
|
||||
offsetof(CPUSPARCState, hver));
|
||||
tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
|
||||
break;
|
||||
case 31: // hstick_cmpr
|
||||
tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
|
||||
tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, hstick_cmpr));
|
||||
tcg_gen_st_i32(cpu_tmp32, cpu_env,
|
||||
offsetof(CPUSPARCState, hstick_cmpr));
|
||||
break;
|
||||
default:
|
||||
goto illegal_insn;
|
||||
|
|
@ -2143,62 +2176,75 @@ static void disas_sparc_insn(DisasContext * dc)
|
|||
}
|
||||
break;
|
||||
case 5: // tba
|
||||
tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, tbr));
|
||||
tcg_gen_ld_tl(cpu_dst, cpu_env,
|
||||
offsetof(CPUSPARCState, tbr));
|
||||
break;
|
||||
case 6: // pstate
|
||||
tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, pstate));
|
||||
tcg_gen_ld_i32(cpu_tmp32, cpu_env,
|
||||
offsetof(CPUSPARCState, pstate));
|
||||
tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
|
||||
break;
|
||||
case 7: // tl
|
||||
tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, tl));
|
||||
tcg_gen_ld_i32(cpu_tmp32, cpu_env,
|
||||
offsetof(CPUSPARCState, tl));
|
||||
tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
|
||||
break;
|
||||
case 8: // pil
|
||||
tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, psrpil));
|
||||
tcg_gen_ld_i32(cpu_tmp32, cpu_env,
|
||||
offsetof(CPUSPARCState, psrpil));
|
||||
tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
|
||||
break;
|
||||
case 9: // cwp
|
||||
tcg_gen_helper_1_0(helper_rdcwp, cpu_dst);
|
||||
break;
|
||||
case 10: // cansave
|
||||
tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, cansave));
|
||||
tcg_gen_ld_i32(cpu_tmp32, cpu_env,
|
||||
offsetof(CPUSPARCState, cansave));
|
||||
tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
|
||||
break;
|
||||
case 11: // canrestore
|
||||
tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, canrestore));
|
||||
tcg_gen_ld_i32(cpu_tmp32, cpu_env,
|
||||
offsetof(CPUSPARCState, canrestore));
|
||||
tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
|
||||
break;
|
||||
case 12: // cleanwin
|
||||
tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, cleanwin));
|
||||
tcg_gen_ld_i32(cpu_tmp32, cpu_env,
|
||||
offsetof(CPUSPARCState, cleanwin));
|
||||
tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
|
||||
break;
|
||||
case 13: // otherwin
|
||||
tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, otherwin));
|
||||
tcg_gen_ld_i32(cpu_tmp32, cpu_env,
|
||||
offsetof(CPUSPARCState, otherwin));
|
||||
tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
|
||||
break;
|
||||
case 14: // wstate
|
||||
tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, wstate));
|
||||
tcg_gen_ld_i32(cpu_tmp32, cpu_env,
|
||||
offsetof(CPUSPARCState, wstate));
|
||||
tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
|
||||
break;
|
||||
case 16: // UA2005 gl
|
||||
tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, gl));
|
||||
tcg_gen_ld_i32(cpu_tmp32, cpu_env,
|
||||
offsetof(CPUSPARCState, gl));
|
||||
tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
|
||||
break;
|
||||
case 26: // UA2005 strand status
|
||||
if (!hypervisor(dc))
|
||||
goto priv_insn;
|
||||
tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ssr));
|
||||
tcg_gen_ld_i32(cpu_tmp32, cpu_env,
|
||||
offsetof(CPUSPARCState, ssr));
|
||||
tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
|
||||
break;
|
||||
case 31: // ver
|
||||
tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, version));
|
||||
tcg_gen_ld_tl(cpu_dst, cpu_env,
|
||||
offsetof(CPUSPARCState, version));
|
||||
break;
|
||||
case 15: // fq
|
||||
default:
|
||||
goto illegal_insn;
|
||||
}
|
||||
#else
|
||||
tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, wim));
|
||||
tcg_gen_ld_i32(cpu_tmp32, cpu_env,
|
||||
offsetof(CPUSPARCState, wim));
|
||||
tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
|
||||
#endif
|
||||
gen_movl_TN_reg(rd, cpu_dst);
|
||||
|
|
@ -2603,8 +2649,10 @@ static void disas_sparc_insn(DisasContext * dc)
|
|||
gen_fcond(r_cond, fcc, cond); \
|
||||
tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, \
|
||||
tcg_const_tl(0), l1); \
|
||||
glue(glue(gen_op_load_fpr_, size_FDQ), T0)(glue(size_FDQ, FPREG(rs2))); \
|
||||
glue(glue(gen_op_store_, size_FDQ), T0_fpr)(glue(size_FDQ, FPREG(rd))); \
|
||||
glue(glue(gen_op_load_fpr_, size_FDQ), T0) \
|
||||
(glue(size_FDQ, FPREG(rs2))); \
|
||||
glue(glue(gen_op_store_, size_FDQ), T0_fpr) \
|
||||
(glue(size_FDQ, FPREG(rd))); \
|
||||
gen_set_label(l1); \
|
||||
}
|
||||
case 0x001: /* V9 fmovscc %fcc0 */
|
||||
|
|
@ -2659,8 +2707,10 @@ static void disas_sparc_insn(DisasContext * dc)
|
|||
gen_cond(r_cond, icc, cond); \
|
||||
tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, \
|
||||
tcg_const_tl(0), l1); \
|
||||
glue(glue(gen_op_load_fpr_, size_FDQ), T0)(glue(size_FDQ, FPREG(rs2))); \
|
||||
glue(glue(gen_op_store_, size_FDQ), T0_fpr)(glue(size_FDQ, FPREG(rd))); \
|
||||
glue(glue(gen_op_load_fpr_, size_FDQ), T0) \
|
||||
(glue(size_FDQ, FPREG(rs2))); \
|
||||
glue(glue(gen_op_store_, size_FDQ), T0_fpr) \
|
||||
(glue(size_FDQ, FPREG(rd))); \
|
||||
gen_set_label(l1); \
|
||||
}
|
||||
|
||||
|
|
@ -2916,13 +2966,15 @@ static void disas_sparc_insn(DisasContext * dc)
|
|||
#endif
|
||||
case 0xe:
|
||||
CHECK_IU_FEATURE(dc, DIV);
|
||||
tcg_gen_helper_1_2(helper_udiv, cpu_dst, cpu_src1, cpu_src2);
|
||||
tcg_gen_helper_1_2(helper_udiv, cpu_dst, cpu_src1,
|
||||
cpu_src2);
|
||||
if (xop & 0x10)
|
||||
gen_op_div_cc(cpu_dst);
|
||||
break;
|
||||
case 0xf:
|
||||
CHECK_IU_FEATURE(dc, DIV);
|
||||
tcg_gen_helper_1_2(helper_sdiv, cpu_dst, cpu_src1, cpu_src2);
|
||||
tcg_gen_helper_1_2(helper_sdiv, cpu_dst, cpu_src1,
|
||||
cpu_src2);
|
||||
if (xop & 0x10)
|
||||
gen_op_div_cc(cpu_dst);
|
||||
break;
|
||||
|
|
@ -2976,7 +3028,8 @@ static void disas_sparc_insn(DisasContext * dc)
|
|||
switch(rd) {
|
||||
case 0: /* wry */
|
||||
tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
|
||||
tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, y));
|
||||
tcg_gen_st_tl(cpu_dst, cpu_env,
|
||||
offsetof(CPUSPARCState, y));
|
||||
break;
|
||||
#ifndef TARGET_SPARC64
|
||||
case 0x01 ... 0x0f: /* undefined in the
|
||||
|
|
@ -2996,12 +3049,14 @@ static void disas_sparc_insn(DisasContext * dc)
|
|||
case 0x3: /* V9 wrasi */
|
||||
tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
|
||||
tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
|
||||
tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, asi));
|
||||
tcg_gen_st_i32(cpu_tmp32, cpu_env,
|
||||
offsetof(CPUSPARCState, asi));
|
||||
break;
|
||||
case 0x6: /* V9 wrfprs */
|
||||
tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
|
||||
tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
|
||||
tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fprs));
|
||||
tcg_gen_st_i32(cpu_tmp32, cpu_env,
|
||||
offsetof(CPUSPARCState, fprs));
|
||||
save_state(dc, cpu_cond);
|
||||
gen_op_next_insn();
|
||||
tcg_gen_exit_tb(0);
|
||||
|
|
@ -3017,7 +3072,8 @@ static void disas_sparc_insn(DisasContext * dc)
|
|||
if (gen_trap_ifnofpu(dc, cpu_cond))
|
||||
goto jmp_insn;
|
||||
tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
|
||||
tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, gsr));
|
||||
tcg_gen_st_tl(cpu_dst, cpu_env,
|
||||
offsetof(CPUSPARCState, gsr));
|
||||
break;
|
||||
case 0x17: /* Tick compare */
|
||||
#if !defined(CONFIG_USER_ONLY)
|
||||
|
|
@ -3029,8 +3085,9 @@ static void disas_sparc_insn(DisasContext * dc)
|
|||
|
||||
tcg_gen_xor_tl(cpu_dst, cpu_src1,
|
||||
cpu_src2);
|
||||
tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState,
|
||||
tick_cmpr));
|
||||
tcg_gen_st_tl(cpu_dst, cpu_env,
|
||||
offsetof(CPUSPARCState,
|
||||
tick_cmpr));
|
||||
r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
|
||||
tcg_gen_ld_ptr(r_tickptr, cpu_env,
|
||||
offsetof(CPUState, tick));
|
||||
|
|
@ -3065,8 +3122,9 @@ static void disas_sparc_insn(DisasContext * dc)
|
|||
|
||||
tcg_gen_xor_tl(cpu_dst, cpu_src1,
|
||||
cpu_src2);
|
||||
tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState,
|
||||
stick_cmpr));
|
||||
tcg_gen_st_tl(cpu_dst, cpu_env,
|
||||
offsetof(CPUSPARCState,
|
||||
stick_cmpr));
|
||||
r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
|
||||
tcg_gen_ld_ptr(r_tickptr, cpu_env,
|
||||
offsetof(CPUState, stick));
|
||||
|
|
@ -3076,7 +3134,8 @@ static void disas_sparc_insn(DisasContext * dc)
|
|||
break;
|
||||
|
||||
case 0x10: /* Performance Control */
|
||||
case 0x11: /* Performance Instrumentation Counter */
|
||||
case 0x11: /* Performance Instrumentation
|
||||
Counter */
|
||||
case 0x12: /* Dispatch Control */
|
||||
case 0x14: /* Softint set */
|
||||
case 0x15: /* Softint clear */
|
||||
|
|
@ -3155,7 +3214,8 @@ static void disas_sparc_insn(DisasContext * dc)
|
|||
tcg_gen_ld_ptr(r_tsptr, cpu_env,
|
||||
offsetof(CPUState, tsptr));
|
||||
tcg_gen_st_tl(cpu_dst, r_tsptr,
|
||||
offsetof(trap_state, tstate));
|
||||
offsetof(trap_state,
|
||||
tstate));
|
||||
}
|
||||
break;
|
||||
case 3: // tt
|
||||
|
|
@ -3181,7 +3241,8 @@ static void disas_sparc_insn(DisasContext * dc)
|
|||
}
|
||||
break;
|
||||
case 5: // tba
|
||||
tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, tbr));
|
||||
tcg_gen_st_tl(cpu_dst, cpu_env,
|
||||
offsetof(CPUSPARCState, tbr));
|
||||
break;
|
||||
case 6: // pstate
|
||||
save_state(dc, cpu_cond);
|
||||
|
|
@ -3192,52 +3253,69 @@ static void disas_sparc_insn(DisasContext * dc)
|
|||
break;
|
||||
case 7: // tl
|
||||
tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
|
||||
tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, tl));
|
||||
tcg_gen_st_i32(cpu_tmp32, cpu_env,
|
||||
offsetof(CPUSPARCState, tl));
|
||||
break;
|
||||
case 8: // pil
|
||||
tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
|
||||
tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, psrpil));
|
||||
tcg_gen_st_i32(cpu_tmp32, cpu_env,
|
||||
offsetof(CPUSPARCState,
|
||||
psrpil));
|
||||
break;
|
||||
case 9: // cwp
|
||||
tcg_gen_helper_0_1(helper_wrcwp, cpu_dst);
|
||||
break;
|
||||
case 10: // cansave
|
||||
tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
|
||||
tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, cansave));
|
||||
tcg_gen_st_i32(cpu_tmp32, cpu_env,
|
||||
offsetof(CPUSPARCState,
|
||||
cansave));
|
||||
break;
|
||||
case 11: // canrestore
|
||||
tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
|
||||
tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, canrestore));
|
||||
tcg_gen_st_i32(cpu_tmp32, cpu_env,
|
||||
offsetof(CPUSPARCState,
|
||||
canrestore));
|
||||
break;
|
||||
case 12: // cleanwin
|
||||
tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
|
||||
tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, cleanwin));
|
||||
tcg_gen_st_i32(cpu_tmp32, cpu_env,
|
||||
offsetof(CPUSPARCState,
|
||||
cleanwin));
|
||||
break;
|
||||
case 13: // otherwin
|
||||
tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
|
||||
tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, otherwin));
|
||||
tcg_gen_st_i32(cpu_tmp32, cpu_env,
|
||||
offsetof(CPUSPARCState,
|
||||
otherwin));
|
||||
break;
|
||||
case 14: // wstate
|
||||
tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
|
||||
tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, wstate));
|
||||
tcg_gen_st_i32(cpu_tmp32, cpu_env,
|
||||
offsetof(CPUSPARCState,
|
||||
wstate));
|
||||
break;
|
||||
case 16: // UA2005 gl
|
||||
tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
|
||||
tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, gl));
|
||||
tcg_gen_st_i32(cpu_tmp32, cpu_env,
|
||||
offsetof(CPUSPARCState, gl));
|
||||
break;
|
||||
case 26: // UA2005 strand status
|
||||
if (!hypervisor(dc))
|
||||
goto priv_insn;
|
||||
tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
|
||||
tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ssr));
|
||||
tcg_gen_st_i32(cpu_tmp32, cpu_env,
|
||||
offsetof(CPUSPARCState, ssr));
|
||||
break;
|
||||
default:
|
||||
goto illegal_insn;
|
||||
}
|
||||
#else
|
||||
tcg_gen_andi_tl(cpu_dst, cpu_dst, ((1 << NWINDOWS) - 1));
|
||||
tcg_gen_andi_tl(cpu_dst, cpu_dst,
|
||||
((1 << NWINDOWS) - 1));
|
||||
tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
|
||||
tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, wim));
|
||||
tcg_gen_st_i32(cpu_tmp32, cpu_env,
|
||||
offsetof(CPUSPARCState, wim));
|
||||
#endif
|
||||
}
|
||||
break;
|
||||
|
|
@ -3247,7 +3325,8 @@ static void disas_sparc_insn(DisasContext * dc)
|
|||
if (!supervisor(dc))
|
||||
goto priv_insn;
|
||||
tcg_gen_xor_tl(cpu_dst, cpu_dst, cpu_src2);
|
||||
tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, tbr));
|
||||
tcg_gen_st_tl(cpu_dst, cpu_env,
|
||||
offsetof(CPUSPARCState, tbr));
|
||||
#else
|
||||
if (!hypervisor(dc))
|
||||
goto priv_insn;
|
||||
|
|
@ -3265,18 +3344,21 @@ static void disas_sparc_insn(DisasContext * dc)
|
|||
break;
|
||||
case 3: // hintp
|
||||
tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
|
||||
tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, hintp));
|
||||
tcg_gen_st_i32(cpu_tmp32, cpu_env,
|
||||
offsetof(CPUSPARCState, hintp));
|
||||
break;
|
||||
case 5: // htba
|
||||
tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
|
||||
tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, htba));
|
||||
tcg_gen_st_i32(cpu_tmp32, cpu_env,
|
||||
offsetof(CPUSPARCState, htba));
|
||||
break;
|
||||
case 31: // hstick_cmpr
|
||||
{
|
||||
TCGv r_tickptr;
|
||||
|
||||
tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState,
|
||||
hstick_cmpr));
|
||||
tcg_gen_st_tl(cpu_dst, cpu_env,
|
||||
offsetof(CPUSPARCState,
|
||||
hstick_cmpr));
|
||||
r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
|
||||
tcg_gen_ld_ptr(r_tickptr, cpu_env,
|
||||
offsetof(CPUState, hstick));
|
||||
|
|
@ -3854,7 +3936,8 @@ static void disas_sparc_insn(DisasContext * dc)
|
|||
}
|
||||
tcg_gen_helper_0_0(helper_restore);
|
||||
gen_mov_pc_npc(dc, cpu_cond);
|
||||
tcg_gen_helper_0_2(helper_check_align, cpu_dst, tcg_const_i32(3));
|
||||
tcg_gen_helper_0_2(helper_check_align, cpu_dst,
|
||||
tcg_const_i32(3));
|
||||
tcg_gen_mov_tl(cpu_npc, cpu_dst);
|
||||
dc->npc = DYNAMIC_PC;
|
||||
goto jmp_insn;
|
||||
|
|
@ -3877,7 +3960,8 @@ static void disas_sparc_insn(DisasContext * dc)
|
|||
{
|
||||
gen_movl_TN_reg(rd, tcg_const_tl(dc->pc));
|
||||
gen_mov_pc_npc(dc, cpu_cond);
|
||||
tcg_gen_helper_0_2(helper_check_align, cpu_dst, tcg_const_i32(3));
|
||||
tcg_gen_helper_0_2(helper_check_align, cpu_dst,
|
||||
tcg_const_i32(3));
|
||||
tcg_gen_mov_tl(cpu_npc, cpu_dst);
|
||||
dc->npc = DYNAMIC_PC;
|
||||
}
|
||||
|
|
@ -3888,7 +3972,8 @@ static void disas_sparc_insn(DisasContext * dc)
|
|||
if (!supervisor(dc))
|
||||
goto priv_insn;
|
||||
gen_mov_pc_npc(dc, cpu_cond);
|
||||
tcg_gen_helper_0_2(helper_check_align, cpu_dst, tcg_const_i32(3));
|
||||
tcg_gen_helper_0_2(helper_check_align, cpu_dst,
|
||||
tcg_const_i32(3));
|
||||
tcg_gen_mov_tl(cpu_npc, cpu_dst);
|
||||
dc->npc = DYNAMIC_PC;
|
||||
tcg_gen_helper_0_0(helper_rett);
|
||||
|
|
@ -4006,9 +4091,11 @@ static void disas_sparc_insn(DisasContext * dc)
|
|||
case 0xd: /* ldstub -- XXX: should be atomically */
|
||||
ABI32_MASK(cpu_addr);
|
||||
tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
|
||||
tcg_gen_qemu_st8(tcg_const_tl(0xff), cpu_addr, dc->mem_idx);
|
||||
tcg_gen_qemu_st8(tcg_const_tl(0xff), cpu_addr,
|
||||
dc->mem_idx);
|
||||
break;
|
||||
case 0x0f: /* swap register with memory. Also atomically */
|
||||
case 0x0f: /* swap register with memory. Also
|
||||
atomically */
|
||||
CHECK_IU_FEATURE(dc, SWAP);
|
||||
gen_movl_reg_TN(rd, cpu_val);
|
||||
ABI32_MASK(cpu_addr);
|
||||
|
|
@ -4090,7 +4177,8 @@ static void disas_sparc_insn(DisasContext * dc)
|
|||
save_state(dc, cpu_cond);
|
||||
gen_ldstub_asi(cpu_val, cpu_addr, insn);
|
||||
break;
|
||||
case 0x1f: /* swap reg with alt. memory. Also atomically */
|
||||
case 0x1f: /* swap reg with alt. memory. Also
|
||||
atomically */
|
||||
CHECK_IU_FEATURE(dc, SWAP);
|
||||
#ifndef TARGET_SPARC64
|
||||
if (IS_IMM)
|
||||
|
|
@ -4581,7 +4669,8 @@ void gen_intermediate_code_init(CPUSPARCState *env)
|
|||
cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
|
||||
TCG_AREG0, offsetof(CPUState, t1), "T1");
|
||||
cpu_cond = tcg_global_mem_new(TCG_TYPE_TL,
|
||||
TCG_AREG0, offsetof(CPUState, cond), "cond");
|
||||
TCG_AREG0, offsetof(CPUState, cond),
|
||||
"cond");
|
||||
cpu_cc_src = tcg_global_mem_new(TCG_TYPE_TL,
|
||||
TCG_AREG0, offsetof(CPUState, cc_src),
|
||||
"cc_src");
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue