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target-arm: Add QOM subclasses for each ARM cpu implementation

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Register subclasses for each ARM CPU implementation.

Let arm_cpu_list() enumerate CPU subclasses in alphabetical order,
except for special value "any".

Replace cpu_arm_find_by_name()'s string -> CPUID lookup by storing the
CPUID (aka MIDR, Main ID Register) value in the class.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2012-04-20 17:58:31 +00:00
parent ce854d7cc3
commit 777dc78411
3 changed files with 282 additions and 65 deletions
Download patch file Download diff file Expand all files Collapse all files

226
target-arm/cpu.c
View file

@ -34,6 +34,211 @@ static void arm_cpu_reset(CPUState *s)
cpu_state_reset(&cpu->env);
}
static void arm_cpu_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
cpu_exec_init(&cpu->env);
}
/* CPU models */
static void arm926_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
cpu->midr = ARM_CPUID_ARM926;
}
static void arm946_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
cpu->midr = ARM_CPUID_ARM946;
}
static void arm1026_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
cpu->midr = ARM_CPUID_ARM1026;
}
static void arm1136_r2_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
cpu->midr = ARM_CPUID_ARM1136_R2;
}
static void arm1136_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
cpu->midr = ARM_CPUID_ARM1136;
}
static void arm1176_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
cpu->midr = ARM_CPUID_ARM1176;
}
static void arm11mpcore_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
cpu->midr = ARM_CPUID_ARM11MPCORE;
}
static void cortex_m3_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
cpu->midr = ARM_CPUID_CORTEXM3;
}
static void cortex_a8_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
cpu->midr = ARM_CPUID_CORTEXA8;
}
static void cortex_a9_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
cpu->midr = ARM_CPUID_CORTEXA9;
}
static void cortex_a15_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
cpu->midr = ARM_CPUID_CORTEXA15;
}
static void ti925t_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
cpu->midr = ARM_CPUID_TI925T;
}
static void sa1100_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
cpu->midr = ARM_CPUID_SA1100;
}
static void sa1110_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
cpu->midr = ARM_CPUID_SA1110;
}
static void pxa250_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
cpu->midr = ARM_CPUID_PXA250;
}
static void pxa255_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
cpu->midr = ARM_CPUID_PXA255;
}
static void pxa260_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
cpu->midr = ARM_CPUID_PXA260;
}
static void pxa261_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
cpu->midr = ARM_CPUID_PXA261;
}
static void pxa262_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
cpu->midr = ARM_CPUID_PXA262;
}
static void pxa270a0_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
cpu->midr = ARM_CPUID_PXA270_A0;
}
static void pxa270a1_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
cpu->midr = ARM_CPUID_PXA270_A1;
}
static void pxa270b0_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
cpu->midr = ARM_CPUID_PXA270_B0;
}
static void pxa270b1_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
cpu->midr = ARM_CPUID_PXA270_B1;
}
static void pxa270c0_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
cpu->midr = ARM_CPUID_PXA270_C0;
}
static void pxa270c5_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
cpu->midr = ARM_CPUID_PXA270_C5;
}
static void arm_any_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
cpu->midr = ARM_CPUID_ANY;
}
typedef struct ARMCPUInfo {
const char *name;
void (*initfn)(Object *obj);
} ARMCPUInfo;
static const ARMCPUInfo arm_cpus[] = {
{ .name = "arm926", .initfn = arm926_initfn },
{ .name = "arm946", .initfn = arm946_initfn },
{ .name = "arm1026", .initfn = arm1026_initfn },
/* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
* older core than plain "arm1136". In particular this does not
* have the v6K features.
*/
{ .name = "arm1136-r2", .initfn = arm1136_r2_initfn },
{ .name = "arm1136", .initfn = arm1136_initfn },
{ .name = "arm1176", .initfn = arm1176_initfn },
{ .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
{ .name = "cortex-m3", .initfn = cortex_m3_initfn },
{ .name = "cortex-a8", .initfn = cortex_a8_initfn },
{ .name = "cortex-a9", .initfn = cortex_a9_initfn },
{ .name = "cortex-a15", .initfn = cortex_a15_initfn },
{ .name = "ti925t", .initfn = ti925t_initfn },
{ .name = "sa1100", .initfn = sa1100_initfn },
{ .name = "sa1110", .initfn = sa1110_initfn },
{ .name = "pxa250", .initfn = pxa250_initfn },
{ .name = "pxa255", .initfn = pxa255_initfn },
{ .name = "pxa260", .initfn = pxa260_initfn },
{ .name = "pxa261", .initfn = pxa261_initfn },
{ .name = "pxa262", .initfn = pxa262_initfn },
/* "pxa270" is an alias for "pxa270-a0" */
{ .name = "pxa270", .initfn = pxa270a0_initfn },
{ .name = "pxa270-a0", .initfn = pxa270a0_initfn },
{ .name = "pxa270-a1", .initfn = pxa270a1_initfn },
{ .name = "pxa270-b0", .initfn = pxa270b0_initfn },
{ .name = "pxa270-b1", .initfn = pxa270b1_initfn },
{ .name = "pxa270-c0", .initfn = pxa270c0_initfn },
{ .name = "pxa270-c5", .initfn = pxa270c5_initfn },
{ .name = "any", .initfn = arm_any_initfn },
};
static void arm_cpu_class_init(ObjectClass *oc, void *data)
{
ARMCPUClass *acc = ARM_CPU_CLASS(oc);
@ -43,18 +248,37 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->reset = arm_cpu_reset;
}
static void cpu_register(const ARMCPUInfo *info)
{
TypeInfo type_info = {
.name = info->name,
.parent = TYPE_ARM_CPU,
.instance_size = sizeof(ARMCPU),
.instance_init = info->initfn,
.class_size = sizeof(ARMCPUClass),
};
type_register_static(&type_info);
}
static const TypeInfo arm_cpu_type_info = {
.name = TYPE_ARM_CPU,
.parent = TYPE_CPU,
.instance_size = sizeof(ARMCPU),
.abstract = false,
.instance_init = arm_cpu_initfn,
.abstract = true,
.class_size = sizeof(ARMCPUClass),
.class_init = arm_cpu_class_init,
};
static void arm_cpu_register_types(void)
{
int i;
type_register_static(&arm_cpu_type_info);
for (i = 0; i < ARRAY_SIZE(arm_cpus); i++) {
cpu_register(&arm_cpus[i]);
}
}
type_init(arm_cpu_register_types)