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target/riscv: rvk: add CSR support for Zkr

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- add SEED CSR which must be accessed with a read-write instruction:
   A read-only instruction such as CSRRS/CSRRC with rs1=x0 or CSRRSI/CSRRCI
with uimm=0 will raise an illegal instruction exception.
 - add USEED, SSEED fields for MSECCFG CSR

Co-authored-by: Ruibo Lu <luruibo2000@163.com>
Co-authored-by: Zewen Ye <lustrew@foxmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220423023510.30794-13-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Weiwei Li 2022-04-23 10:35:08 +08:00 • committed by Alistair Francis
parent 0976083d1b
commit 77442380ec
4 changed files with 103 additions and 3 deletions
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8
target/riscv/pmp.h
View file

@ -39,9 +39,11 @@ typedef enum {
} pmp_am_t;
typedef enum {
MSECCFG_MML = 1 << 0,
MSECCFG_MMWP = 1 << 1,
MSECCFG_RLB = 1 << 2
MSECCFG_MML = 1 << 0,
MSECCFG_MMWP = 1 << 1,
MSECCFG_RLB = 1 << 2,
MSECCFG_USEED = 1 << 8,
MSECCFG_SSEED = 1 << 9
} mseccfg_field_t;
typedef struct {