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apic, i386/tcg: add x2apic transitions

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This commit adds support for x2APIC transitions when writing to
MSR_IA32_APICBASE register and finally adds CPUID_EXT_X2APIC to
TCG_EXT_FEATURES.

The set_base in APICCommonClass now returns an integer to indicate error in
execution. apic_set_base return -1 on invalid APIC state transition,
accelerator can use this to raise appropriate exception.

Signed-off-by: Bui Quang Minh <minhquangbui99@gmail.com>
Message-Id: <20240111154404.5333-4-minhquangbui99@gmail.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Bui Quang Minh 2024-01-11 22:44:00 +07:00 • committed by Michael S. Tsirkin
parent b5ee0468e9
commit 774204cf98
10 changed files with 96 additions and 19 deletions
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14
target/i386/tcg/sysemu/misc_helper.c
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@ -158,9 +158,19 @@ void helper_wrmsr(CPUX86State *env)
case MSR_IA32_SYSENTER_EIP:
env->sysenter_eip = val;
break;
case MSR_IA32_APICBASE:
cpu_set_apic_base(env_archcpu(env)->apic_state, val);
case MSR_IA32_APICBASE: {
int ret;
if (val & MSR_IA32_APICBASE_RESERVED) {
goto error;
}
ret = cpu_set_apic_base(env_archcpu(env)->apic_state, val);
if (ret < 0) {
goto error;
}
break;
}
case MSR_EFER:
{
uint64_t update_mask;