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Great PowerPC emulation code resynchronisation and improvments:

Browse source 
- Add status file to make regression tracking easier
- Move all micro-operations helpers definitions into a separate header:
  should never be seen outside of op.c
- Update copyrights
- Add new / missing PowerPC CPU definitions
- Add definitions for PowerPC BookE
- Add support for PowerPC 6xx/7xx software driven TLBs
  Allow use of PowerPC 603 as an example
- Add preliminary code for POWER, POWER2, PowerPC 403, 405, 440, 601, 602
  and BookE support
- Avoid compiling priviledged only resources support for user-mode emulation
- Remove unused helpers / micro-ops / dead code
- Add instructions usage statistics dump: useful to figure which instructions
  need strong optimizations.
- Micro-operation fixes:
  * add missing RETURN in some micro-ops
  * fix prototypes
  * use softfloat routines for all floating-point operations
  * fix tlbie instruction
  * move some huge micro-operations into helpers
- emulation fixes:
  * fix inverted opcodes for fcmpo / fcmpu
  * condition register update is always to be done after the whole
    instruction has completed
  * add missing NIP updates when calling helpers that may generate an
    exception
- optimizations and improvments:
  * optimize very often used instructions (li, mr, rlwixx...)
  * remove specific micro-ops for rarely used instructions
  * add routines for addresses computations to avoid bugs due to multiple
    different implementations
  * fix TB linking: do not reset T0 at the end of every TB.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2473 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
j_mayer 2007-03-07 08:32:30 +00:00
parent 1c7b3754f6
commit 76a66253e5
19 changed files with 7671 additions and 2596 deletions
Download patch file Download diff file Expand all files Collapse all files

3
cpu-all.h
View file

@ -759,6 +759,9 @@ CPUState *cpu_copy(CPUState *env);
void cpu_dump_state(CPUState *env, FILE *f,
int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
int flags);
void cpu_dump_statistics (CPUState *env, FILE *f,
int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
int flags);
void cpu_abort(CPUState *env, const char *fmt, ...);
extern CPUState *first_cpu;

4
gdbstub.c
View file

@ -307,7 +307,7 @@ static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
registers[98] = tswapl(tmp);
registers[99] = tswapl(env->lr);
registers[100] = tswapl(env->ctr);
registers[101] = tswapl(do_load_xer(env));
registers[101] = tswapl(ppc_load_xer(env));
registers[102] = 0;
return 103 * 4;
@ -335,7 +335,7 @@ static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
env->crf[i] = (registers[98] >> (32 - ((i + 1) * 4))) & 0xF;
env->lr = tswapl(registers[99]);
env->ctr = tswapl(registers[100]);
do_store_xer(env, tswapl(registers[101]));
ppc_store_xer(env, tswapl(registers[101]));
}
#elif defined (TARGET_SPARC)
static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)

51
hw/ppc.c
View file

@ -1,7 +1,7 @@
/*
* QEMU generic PPC hardware System Emulator
*
* Copyright (c) 2003-2004 Jocelyn Mayer
* Copyright (c) 2003-2007 Jocelyn Mayer
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -75,6 +75,7 @@ uint32_t cpu_ppc_load_tbu (CPUState *env)
#ifdef DEBUG_TB
printf("%s: tb=0x%016lx\n", __func__, tb);
#endif
return tb >> 32;
}
@ -117,6 +118,7 @@ uint32_t cpu_ppc_load_decr (CPUState *env)
#if defined(DEBUG_TB)
printf("%s: 0x%08x\n", __func__, decr);
#endif
return decr;
}
@ -181,7 +183,7 @@ ppc_tb_t *cpu_ppc_tb_init (CPUState *env, uint32_t freq)
/* Create new timer */
tb_env->decr_timer =
qemu_new_timer(vm_clock, &cpu_ppc_decr_cb, env);
/* There is a bug in 2.4 kernels:
/* There is a bug in Linux 2.4 kernels:
* if a decrementer exception is pending when it enables msr_ee,
* it's not ready to handle it...
*/
@ -191,6 +193,50 @@ ppc_tb_t *cpu_ppc_tb_init (CPUState *env, uint32_t freq)
return tb_env;
}
/* Specific helpers for POWER & PowerPC 601 RTC */
ppc_tb_t *cpu_ppc601_rtc_init (CPUState *env)
{
return cpu_ppc_tb_init(env, 7812500);
}
void cpu_ppc601_store_rtcu (CPUState *env, uint32_t value)
__attribute__ (( alias ("cpu_ppc_store_tbu") ));
uint32_t cpu_ppc601_load_rtcu (CPUState *env)
__attribute__ (( alias ("cpu_ppc_load_tbu") ));
void cpu_ppc601_store_rtcl (CPUState *env, uint32_t value)
{
cpu_ppc_store_tbl(env, value & 0x3FFFFF80);
}
uint32_t cpu_ppc601_load_rtcl (CPUState *env)
{
return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
}
/* Embedded PowerPC timers */
target_ulong load_40x_pit (CPUState *env)
{
/* XXX: TODO */
return 0;
}
void store_40x_pit (CPUState *env, target_ulong val)
{
/* XXX: TODO */
}
void store_booke_tcr (CPUState *env, target_ulong val)
{
/* XXX: TODO */
}
void store_booke_tsr (CPUState *env, target_ulong val)
{
/* XXX: TODO */
}
#if 0
/*****************************************************************************/
/* Handle system reset (for now, just stop emulation) */
@ -264,6 +310,7 @@ uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr)
tmp |= m48t59_read(nvram, addr + 1) << 16;
tmp |= m48t59_read(nvram, addr + 2) << 8;
tmp |= m48t59_read(nvram, addr + 3);
return tmp;
}

15
linux-user/main.c
View file

@ -671,15 +671,20 @@ void cpu_ppc_store_tbl (CPUState *env, uint32_t value)
cpu_ppc_store_tb(env, ((uint64_t)cpu_ppc_load_tbl(env) << 32) | value);
}
uint32_t cpu_ppc_load_decr (CPUState *env)
void cpu_ppc601_store_rtcu (CPUState *env, uint32_t value)
__attribute__ (( alias ("cpu_ppc_store_tbu") ));
uint32_t cpu_ppc601_load_rtcu (CPUState *env)
__attribute__ (( alias ("cpu_ppc_load_tbu") ));
void cpu_ppc601_store_rtcl (CPUState *env, uint32_t value)
{
/* TO FIX */
return -1;
cpu_ppc_store_tbl(env, value & 0x3FFFFF80);
}
void cpu_ppc_store_decr (CPUState *env, uint32_t value)
uint32_t cpu_ppc601_load_rtcl (CPUState *env)
{
/* TO FIX */
return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
}
void cpu_loop(CPUPPCState *env)

15
monitor.c
View file

@ -331,6 +331,17 @@ static void do_info_history (void)
}
}
#if defined(TARGET_PPC)
/* XXX: not implemented in other targets */
static void do_info_cpu_stats (void)
{
CPUState *env;
env = mon_get_cpu();
cpu_dump_statistics(env, NULL, &monitor_fprintf, 0);
}
#endif
static void do_quit(void)
{
exit(0);
@ -1303,6 +1314,10 @@ static term_cmd_t info_cmds[] = {
"", "show which guest mouse is receiving events" },
{ "vnc", "", do_info_vnc,
"", "show the vnc server status"},
#if defined(TARGET_PPC)
{ "cpustats", "", do_info_cpu_stats,
"", "show CPU statistics", },
#endif
{ NULL, NULL, },
};

91
target-ppc/STATUS Normal file
View file

@ -0,0 +1,91 @@
PowerPC emulation status.
The goal of this file is to provide a reference status to avoid regressions.
===============================================================================
PowerPC core emulation status
PowerPC CPU known to work (ie booting at least Linux 2.4):
* main stream PowerPC cores
- PowerPC 603 & derivatives
- PowerPC 604 & derivatives
- PowerPC 740 & derivatives
- PowerPC 750 & derivatives
PowerPC that should work but are not supported by standard Linux kernel
(then remain mostly untested)
- PowerPC 745
- PowerPC 755
Work in progress:
* embedded PowerPC cores
- PowerPC 405
- BookE PowerPC
- e500 core (Freescale PowerQUICC)
* main stream PowerPC cores
- PowerPC 601
- PowerPC 602
TODO:
* embedded PowerPC cores
- PowerPC 401
- PowerPC 403
- PowerPC 440
- PowerPC 460
* main stream PowerPC cores
- PowerPC 7400 (aka G4)
- PowerPC 7410
- PowerPC 7450
- PowerPC 7455
- PowerPC 7457
- PowerPC 7457A
* original POWER
- POWER
- POWER2
* 64 bits PowerPC cores
- PowerPC 620
- PowerPC 630 (aka POWER3)
- PowerPC 631 (aka POWER3+)
- POWER4
- POWER4+
- POWER5
- POWER5+
- PowerPC 970
* RS64 series
- RS64
- RS64-II
- RS64-III
- RS64-IV
===============================================================================
PowerPC microcontrollers emulation status
TODO:
- PowerPC 40x microcontrollers emulation
- PowerQUICC microcontrollers emulation
===============================================================================
PowerPC based platforms emulation status
* PREP platform (RS/6000 7043...) - TO BE CHECKED (broken)
- Gentoo Linux live CDROM 1.4
- Debian Linux 3.0
- Mandrake Linux 9
* heathrow PowerMac platform (beige PowerMac) - TO BE CHECKED (broken)
- Gentoo Linux live CDROM 1.4
- Debian Linux 3.0
- Mandrake Linux 9
* mac99 platform (white and blue PowerMac, ...)
- Gentoo Linux live CDROM 1.4 - boots, compiles linux kernel
- Debian Linux woody - boots from CDROM and HDD
- Mandrake Linux 9 - boots from CDROM, freezes during install
TODO:
- MCA based RS/6000 emulation
- CHRP emulation (not PowerMac)
- PPAR emulation
- misc PowerPC reference boards emulation
===============================================================================
(to be completed)

460
target-ppc/cpu.h
View file

@ -1,7 +1,7 @@
/*
* PowerPC emulation cpu definitions for qemu.
*
* Copyright (c) 2003-2005 Jocelyn Mayer
* Copyright (c) 2003-2007 Jocelyn Mayer
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
@ -21,8 +21,22 @@
#define __CPU_PPC_H__
#include "config.h"
#include <stdint.h>
#if defined (TARGET_PPC64)
typedef uint64_t ppc_gpr_t;
#define TARGET_LONG_BITS 64
#define REGX "%016" PRIx64
#elif defined(TARGET_E500)
/* GPR are 64 bits: used by vector extension */
typedef uint64_t ppc_gpr_t;
#define TARGET_LONG_BITS 32
#define REGX "%08" PRIx32
#else
typedef uint32_t ppc_gpr_t;
#define TARGET_LONG_BITS 32
#define REGX "%08" PRIx32
#endif
#include "cpu-defs.h"
@ -32,7 +46,11 @@
#define TARGET_HAS_ICE 1
#if defined (TARGET_PPC64)
#define ELF_MACHINE EM_PPC64
#else
#define ELF_MACHINE EM_PPC
#endif
/* XXX: this should be tunable: PowerPC 601 & 64 bits PowerPC
* have different cache line sizes
@ -42,6 +60,7 @@
/* XXX: put this in a common place */
#define likely(x) __builtin_expect(!!(x), 1)
#define unlikely(x) __builtin_expect(!!(x), 0)
/*****************************************************************************/
/* PVR definitions for most known PowerPC */
@ -54,72 +73,155 @@ enum {
CPU_PPC_401E2 = 0x00250000,
CPU_PPC_401F2 = 0x00260000,
CPU_PPC_401G2 = 0x00270000,
CPU_PPC_IOP480 = 0x40100000,
#define CPU_PPC_401 CPU_PPC_401G2
CPU_PPC_IOP480 = 0x40100000, /* 401B2 ? */
CPU_PPC_COBRA = 0x10100000, /* IBM Processor for Network Resources */
/* PowerPC 403 cores */
CPU_PPC_403GA = 0x00200000,
CPU_PPC_403GA = 0x00200011,
CPU_PPC_403GB = 0x00200100,
CPU_PPC_403GC = 0x00200200,
CPU_PPC_403GCX = 0x00201400,
#define CPU_PPC_403 CPU_PPC_403GCX
/* PowerPC 405 cores */
CPU_PPC_405 = 0x40110000,
CPU_PPC_405EP = 0x51210000,
CPU_PPC_405GPR = 0x50910000,
CPU_PPC_405CR = 0x40110145,
#define CPU_PPC_405GP CPU_PPC_405CR
CPU_PPC_405EP = 0x51210950,
CPU_PPC_405GPR = 0x50910951,
CPU_PPC_405D2 = 0x20010000,
CPU_PPC_405D4 = 0x41810000,
CPU_PPC_NPE405H = 0x41410000,
CPU_PPC_NPE405L = 0x41610000,
#define CPU_PPC_405 CPU_PPC_405D4
CPU_PPC_NPE405H = 0x414100C0,
CPU_PPC_NPE405H2 = 0x41410140,
CPU_PPC_NPE405L = 0x416100C0,
/* XXX: missing 405LP, LC77700 */
/* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
#if 0
CPU_PPC_STB02 = xxx,
CPU_PPC_STB01000 = xxx,
#endif
#if 0
CPU_PPC_STB01010 = xxx,
#endif
#if 0
CPU_PPC_STB0210 = xxx,
#endif
CPU_PPC_STB03 = 0x40310000,
#if 0
CPU_PPC_STB04 = xxx,
CPU_PPC_STB043 = xxx,
#endif
CPU_PPC_STB25 = 0x51510000,
#if 0
CPU_PPC_STB045 = xxx,
#endif
CPU_PPC_STB25 = 0x51510950,
#if 0
CPU_PPC_STB130 = xxx,
#endif
/* Xilinx cores */
CPU_PPC_X2VP4 = 0x20010820,
#define CPU_PPC_X2VP7 CPU_PPC_X2VP4
CPU_PPC_X2VP20 = 0x20010860,
#define CPU_PPC_X2VP50 CPU_PPC_X2VP20
/* PowerPC 440 cores */
CPU_PPC_440EP = 0x42220000,
CPU_PPC_440GP = 0x40120400,
CPU_PPC_440GX = 0x51B20000,
/* PowerPC MPC 8xx cores */
CPU_PPC_8540 = 0x80200000,
CPU_PPC_440EP = 0x422218D3,
#define CPU_PPC_440GR CPU_PPC_440EP
CPU_PPC_440GP = 0x40120481,
CPU_PPC_440GX = 0x51B21850,
CPU_PPC_440GXc = 0x51B21892,
CPU_PPC_440GXf = 0x51B21894,
CPU_PPC_440SP = 0x53221850,
CPU_PPC_440SP2 = 0x53221891,
CPU_PPC_440SPE = 0x53421890,
/* XXX: missing 440GRX */
/* PowerPC 460 cores - TODO */
/* PowerPC MPC 5xx cores */
CPU_PPC_5xx = 0x00020020,
/* PowerPC MPC 8xx cores (aka PowerQUICC) */
CPU_PPC_8xx = 0x00500000,
CPU_PPC_8240 = 0x00810100,
CPU_PPC_8245 = 0x00811014,
/* PowerPC MPC 8xxx cores (aka PowerQUICC-II) */
CPU_PPC_82xx_HIP3 = 0x00810101,
CPU_PPC_82xx_HIP4 = 0x80811014,
CPU_PPC_827x = 0x80822013,
/* eCores */
CPU_PPC_e200 = 0x81120000,
CPU_PPC_e500v110 = 0x80200010,
CPU_PPC_e500v120 = 0x80200020,
CPU_PPC_e500v210 = 0x80210010,
CPU_PPC_e500v220 = 0x80210020,
#define CPU_PPC_e500 CPU_PPC_e500v220
CPU_PPC_e600 = 0x80040010,
/* PowerPC 6xx cores */
CPU_PPC_601 = 0x00010000,
CPU_PPC_602 = 0x00050000,
CPU_PPC_603 = 0x00030000,
CPU_PPC_603E = 0x00060000,
CPU_PPC_603EV = 0x00070000,
CPU_PPC_603R = 0x00071000,
CPU_PPC_G2 = 0x80810000,
CPU_PPC_G2LE = 0x80820000,
CPU_PPC_601 = 0x00010001,
CPU_PPC_602 = 0x00050100,
CPU_PPC_603 = 0x00030100,
CPU_PPC_603E = 0x00060101,
CPU_PPC_603P = 0x00070000,
CPU_PPC_603E7v = 0x00070100,
CPU_PPC_603E7v2 = 0x00070201,
CPU_PPC_603E7 = 0x00070200,
CPU_PPC_603R = 0x00071201,
CPU_PPC_G2 = 0x00810011,
CPU_PPC_G2H4 = 0x80811010,
CPU_PPC_G2gp = 0x80821010,
CPU_PPC_G2ls = 0x90810010,
CPU_PPC_G2LE = 0x80820010,
CPU_PPC_G2LEgp = 0x80822010,
CPU_PPC_G2LEls = 0xA0822010,
CPU_PPC_604 = 0x00040000,
CPU_PPC_604E = 0x00090000,
CPU_PPC_604R = 0x000a0000,
CPU_PPC_604E = 0x00090100, /* Also 2110 & 2120 */
CPU_PPC_604R = 0x000a0101,
/* PowerPC 74x/75x cores (aka G3) */
CPU_PPC_74x = 0x00080000,
CPU_PPC_755 = 0x00083000,
CPU_PPC_740E = 0x00080100,
CPU_PPC_750E = 0x00080200,
CPU_PPC_755_10 = 0x00083100,
CPU_PPC_755_11 = 0x00083101,
CPU_PPC_755_20 = 0x00083200,
CPU_PPC_755D = 0x00083202,
CPU_PPC_755E = 0x00083203,
#define CPU_PPC_755 CPU_PPC_755E
CPU_PPC_74xP = 0x10080000,
CPU_PPC_750CXE22 = 0x00082202,
CPU_PPC_750CXE21 = 0x00082201,
CPU_PPC_750CXE22 = 0x00082212,
CPU_PPC_750CXE23 = 0x00082203,
CPU_PPC_750CXE24 = 0x00082214,
CPU_PPC_750CXE24b = 0x00083214,
CPU_PPC_750CXE31 = 0x00083211,
CPU_PPC_750CXE31b = 0x00083311,
#define CPU_PPC_750CXE CPU_PPC_750CXE31b
CPU_PPC_750FX = 0x70000000,
CPU_PPC_750GX = 0x70020000,
CPU_PPC_750CXR = 0x00083410,
CPU_PPC_750FX10 = 0x70000100,
CPU_PPC_750FX20 = 0x70000200,
CPU_PPC_750FX21 = 0x70000201,
CPU_PPC_750FX22 = 0x70000202,
CPU_PPC_750FX23 = 0x70000203,
#define CPU_PPC_750FX CPU_PPC_750FX23
CPU_PPC_750FL = 0x700A0203,
CPU_PPC_750GX10 = 0x70020100,
CPU_PPC_750GX11 = 0x70020101,
CPU_PPC_750GX12 = 0x70020102,
#define CPU_PPC_750GX CPU_PPC_750GX12
CPU_PPC_750GL = 0x70020102,
CPU_PPC_750L30 = 0x00088300,
CPU_PPC_750L32 = 0x00088302,
CPU_PPC_750CL = 0x00087200,
/* PowerPC 74xx cores (aka G4) */
CPU_PPC_7400 = 0x000C0000,
CPU_PPC_7410 = 0x800C0000,
CPU_PPC_7441 = 0x80000200,
CPU_PPC_7450 = 0x80000000,
CPU_PPC_7400 = 0x000C0100,
CPU_PPC_7410C = 0x800C1102,
CPU_PPC_7410D = 0x800C1103,
CPU_PPC_7410E = 0x800C1104,
CPU_PPC_7441 = 0x80000210,
CPU_PPC_7445 = 0x80010100,
CPU_PPC_7447 = 0x80020100,
CPU_PPC_7447A = 0x80030101,
CPU_PPC_7448 = 0x80040100,
CPU_PPC_7450 = 0x80000200,
CPU_PPC_7450b = 0x80000201,
CPU_PPC_7451 = 0x80000203,
CPU_PPC_7455 = 0x80010000,
CPU_PPC_7457 = 0x80020000,
CPU_PPC_7451G = 0x80000210,
CPU_PPC_7455 = 0x80010201,
CPU_PPC_7455F = 0x80010303,
CPU_PPC_7455G = 0x80010304,
CPU_PPC_7457 = 0x80020101,
CPU_PPC_7457C = 0x80020102,
CPU_PPC_7457A = 0x80030000,
/* 64 bits PowerPC */
CPU_PPC_620 = 0x00140000,
@ -130,7 +232,21 @@ enum {
CPU_PPC_POWER5 = 0x003A0000,
CPU_PPC_POWER5P = 0x003B0000,
CPU_PPC_970 = 0x00390000,
CPU_PPC_970FX = 0x003C0000,
CPU_PPC_970FX10 = 0x00391100,
CPU_PPC_970FX20 = 0x003C0200,
CPU_PPC_970FX21 = 0x003C0201,
CPU_PPC_970FX30 = 0x003C0300,
CPU_PPC_970FX31 = 0x003C0301,
#define CPU_PPC_970FX CPU_PPC_970FX31
CPU_PPC_970MP10 = 0x00440100,
CPU_PPC_970MP11 = 0x00440101,
#define CPU_PPC_970MP CPU_PPC_970MP11
CPU_PPC_CELL10 = 0x00700100,
CPU_PPC_CELL20 = 0x00700400,
CPU_PPC_CELL30 = 0x00700500,
CPU_PPC_CELL31 = 0x00700501,
#define CPU_PPC_CELL32 CPU_PPC_CELL31
#define CPU_PPC_CELL CPU_PPC_CELL32
CPU_PPC_RS64 = 0x00330000,
CPU_PPC_RS64II = 0x00340000,
CPU_PPC_RS64III = 0x00360000,
@ -147,12 +263,28 @@ enum {
#endif
};
/* System version register (used on MPC 8xx) */
/* System version register (used on MPC 8xxx) */
enum {
PPC_SVR_8540 = 0x80300000,
PPC_SVR_8541E = 0x807A0000,
PPC_SVR_8555E = 0x80790000,
PPC_SVR_8560 = 0x80700000,
PPC_SVR_8541E = 0x807A0010,
PPC_SVR_8543v10 = 0x80320010,
PPC_SVR_8543v11 = 0x80320011,
PPC_SVR_8543v20 = 0x80320020,
PPC_SVR_8543Ev10 = 0x803A0010,
PPC_SVR_8543Ev11 = 0x803A0011,
PPC_SVR_8543Ev20 = 0x803A0020,
PPC_SVR_8545 = 0x80310220,
PPC_SVR_8545E = 0x80390220,
PPC_SVR_8547E = 0x80390120,
PPC_SCR_8548v10 = 0x80310010,
PPC_SCR_8548v11 = 0x80310011,
PPC_SCR_8548v20 = 0x80310020,
PPC_SVR_8548Ev10 = 0x80390010,
PPC_SVR_8548Ev11 = 0x80390011,
PPC_SVR_8548Ev20 = 0x80390020,
PPC_SVR_8555E = 0x80790010,
PPC_SVR_8560v10 = 0x80700010,
PPC_SVR_8560v20 = 0x80700020,
};
/*****************************************************************************/
@ -197,7 +329,7 @@ enum {
/* Time base support */
PPC_TB = 0x00002000,
/* Embedded PowerPC dedicated instructions */
PPC_4xx_COMMON = 0x00004000,
PPC_EMB_COMMON = 0x00004000,
/* PowerPC 40x exception model */
PPC_40x_EXCP = 0x00008000,
/* PowerPC 40x specific instructions */
@ -225,12 +357,20 @@ enum {
PPC_64H = 0x02000000,
/* 64 bits PowerPC "bridge" features */
PPC_64_BRIDGE = 0x04000000,
/* BookE (embedded) PowerPC specification */
PPC_BOOKE = 0x08000000,
/* eieio */
PPC_MEM_EIEIO = 0x10000000,
/* e500 vector instructions */
PPC_E500_VECTOR = 0x20000000,
/* PowerPC 4xx dedicated instructions */
PPC_4xx_COMMON = 0x40000000,
};
/* CPU run-time flags (MMU and exception model) */
enum {
/* MMU model */
#define PPC_FLAGS_MMU_MASK (0x0000000F)
PPC_FLAGS_MMU_MASK = 0x0000000F,
/* Standard 32 bits PowerPC MMU */
PPC_FLAGS_MMU_32B = 0x00000000,
/* Standard 64 bits PowerPC MMU */
@ -243,8 +383,10 @@ enum {
PPC_FLAGS_MMU_SOFT_4xx = 0x00000004,
/* PowerPC 403 MMU */
PPC_FLAGS_MMU_403 = 0x00000005,
/* Freescale e500 MMU model */
PPC_FLAGS_MMU_e500 = 0x00000006,
/* Exception model */
#define PPC_FLAGS_EXCP_MASK (0x000000F0)
PPC_FLAGS_EXCP_MASK = 0x000000F0,
/* Standard PowerPC exception model */
PPC_FLAGS_EXCP_STD = 0x00000000,
/* PowerPC 40x exception model */
@ -277,32 +419,42 @@ enum {
#define PPC_FLAGS_TODO (0x00000000)
/* PowerPC 40x instruction set */
#define PPC_INSNS_4xx (PPC_INSNS_BASE | PPC_MEM_TLBSYNC | PPC_4xx_COMMON)
#define PPC_INSNS_EMB (PPC_INSNS_BASE | PPC_MEM_TLBSYNC | PPC_EMB_COMMON)
/* PowerPC 401 */
#define PPC_INSNS_401 (PPC_INSNS_TODO)
#define PPC_FLAGS_401 (PPC_FLAGS_TODO)
/* PowerPC 403 */
#define PPC_INSNS_403 (PPC_INSNS_4xx | PPC_MEM_SYNC | PPC_MEM_TLBIA | \
PPC_40x_EXCP | PPC_40x_SPEC)
#define PPC_INSNS_403 (PPC_INSNS_EMB | PPC_MEM_SYNC | PPC_MEM_EIEIO | \
PPC_MEM_TLBIA | PPC_4xx_COMMON | PPC_40x_EXCP | \
PPC_40x_SPEC)
#define PPC_FLAGS_403 (PPC_FLAGS_MMU_403 | PPC_FLAGS_EXCP_40x)
/* PowerPC 405 */
#define PPC_INSNS_405 (PPC_INSNS_4xx | PPC_MEM_SYNC | PPC_CACHE_OPT | \
PPC_MEM_TLBIA | PPC_TB | PPC_40x_SPEC | PPC_40x_EXCP | \
#define PPC_INSNS_405 (PPC_INSNS_EMB | PPC_MEM_SYNC | PPC_MEM_EIEIO | \
PPC_CACHE_OPT | PPC_MEM_TLBIA | PPC_TB | \
PPC_4xx_COMMON | PPC_40x_SPEC | PPC_40x_EXCP | \
PPC_405_MAC)
#define PPC_FLAGS_405 (PPC_FLAGS_MMU_SOFT_4xx | PPC_FLAGS_EXCP_40x)
/* PowerPC 440 */
#define PPC_INSNS_440 (PPC_INSNS_4xx | PPC_CACHE_OPT | PPC_405_MAC | \
PPC_440_SPEC)
#define PPC_INSNS_440 (PPC_INSNS_EMB | PPC_CACHE_OPT | PPC_BOOKE | \
PPC_4xx_COMMON | PPC_405_MAC | PPC_440_SPEC)
#define PPC_FLAGS_440 (PPC_FLAGS_TODO)
/* Generic BookE PowerPC */
#define PPC_INSNS_BOOKE (PPC_INSNS_EMB | PPC_BOOKE | PPC_MEM_EIEIO | \
PPC_FLOAT | PPC_FLOAT_OPT | PPC_CACHE_OPT)
#define PPC_FLAGS_BOOKE (PPC_FLAGS_MMU_SOFT_4xx | PPC_FLAGS_EXCP_40x)
/* e500 core */
#define PPC_INSNS_E500 (PPC_INSNS_EMB | PPC_BOOKE | PPC_MEM_EIEIO | \
PPC_CACHE_OPT | PPC_E500_VECTOR)
#define PPC_FLAGS_E500 (PPC_FLAGS_MMU_SOFT_4xx | PPC_FLAGS_EXCP_40x)
/* Non-embedded PowerPC */
#define PPC_INSNS_COMMON (PPC_INSNS_BASE | PPC_FLOAT | PPC_MEM_SYNC | \
PPC_SEGMENT | PPC_MEM_TLBIE)
PPC_MEM_EIEIO | PPC_SEGMENT | PPC_MEM_TLBIE)
/* PowerPC 601 */
#define PPC_INSNS_601 (PPC_INSNS_COMMON | PPC_EXTERN | PPC_POWER_BR)
#define PPC_FLAGS_601 (PPC_FLAGS_MMU_601 | PPC_FLAGS_EXCP_601)
/* PowerPC 602 */
#define PPC_INSNS_602 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB | \
PPC_MEM_TLBSYNC | PPC_TB)
PPC_MEM_TLBSYNC | PPC_TB | PPC_602_SPEC)
#define PPC_FLAGS_602 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_602)
/* PowerPC 603 */
#define PPC_INSNS_603 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB | \
@ -348,13 +500,17 @@ typedef struct ppc_tb_t ppc_tb_t;
typedef struct ppc_spr_t ppc_spr_t;
typedef struct ppc_dcr_t ppc_dcr_t;
typedef struct ppc_avr_t ppc_avr_t;
typedef struct ppc_tlb_t ppc_tlb_t;
/* SPR access micro-ops generations callbacks */
struct ppc_spr_t {
void (*uea_read)(void *opaque, int spr_num);
void (*uea_write)(void *opaque, int spr_num);
#if !defined(CONFIG_USER_ONLY)
void (*oea_read)(void *opaque, int spr_num);
void (*oea_write)(void *opaque, int spr_num);
#endif
const unsigned char *name;
};
@ -364,46 +520,42 @@ struct ppc_avr_t {
};
/* Software TLB cache */
typedef struct ppc_tlb_t ppc_tlb_t;
struct ppc_tlb_t {
/* Physical page number */
target_phys_addr_t RPN;
/* Virtual page number */
target_ulong VPN;
/* Page size */
target_ulong size;
/* Protection bits */
int prot;
int is_user;
uint32_t private;
uint32_t flags;
target_ulong pte0;
target_ulong pte1;
target_ulong EPN;
target_ulong PID;
int size;
};
/*****************************************************************************/
/* Machine state register bits definition */
#define MSR_SF 63 /* Sixty-four-bit mode */
#define MSR_SF 63 /* Sixty-four-bit mode hflags */
#define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
#define MSR_HV 60 /* hypervisor state */
#define MSR_VR 25 /* altivec available */
#define MSR_AP 23 /* Access privilege state on 602 */
#define MSR_SA 22 /* Supervisor access mode on 602 */
#define MSR_HV 60 /* hypervisor state hflags */
#define MSR_UCLE 26 /* User-mode cache lock enable on e500 */
#define MSR_VR 25 /* altivec available hflags */
#define MSR_SPE 25 /* SPE enable on e500 hflags */
#define MSR_AP 23 /* Access privilege state on 602 hflags */
#define MSR_SA 22 /* Supervisor access mode on 602 hflags */
#define MSR_KEY 19 /* key bit on 603e */
#define MSR_POW 18 /* Power management */
#define MSR_WE 18 /* Wait state enable on embedded PowerPC */
#define MSR_TGPR 17 /* TGPR usage on 602/603 */
#define MSR_TLB 17 /* TLB on ? */
#define MSR_TLB 17 /* TLB update on ? */
#define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC */
#define MSR_ILE 16 /* Interrupt little-endian mode */
#define MSR_EE 15 /* External interrupt enable */
#define MSR_PR 14 /* Problem state */
#define MSR_FP 13 /* Floating point available */
#define MSR_PR 14 /* Problem state hflags */
#define MSR_FP 13 /* Floating point available hflags */
#define MSR_ME 12 /* Machine check interrupt enable */
#define MSR_FE0 11 /* Floating point exception mode 0 */
#define MSR_SE 10 /* Single-step trace enable */
#define MSR_FE0 11 /* Floating point exception mode 0 hflags */
#define MSR_SE 10 /* Single-step trace enable hflags */
#define MSR_DWE 10 /* Debug wait enable on 405 */
#define MSR_BE 9 /* Branch trace enable */
#define MSR_UBLE 10 /* User BTB lock enable on e500 */
#define MSR_BE 9 /* Branch trace enable hflags */
#define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC */
#define MSR_FE1 8 /* Floating point exception mode 1 */
#define MSR_FE1 8 /* Floating point exception mode 1 hflags */
#define MSR_AL 7 /* AL bit on POWER */
#define MSR_IP 6 /* Interrupt prefix */
#define MSR_IR 5 /* Instruction relocate */
@ -415,11 +567,13 @@ struct ppc_tlb_t {
#define MSR_PX 2 /* Protection exclusive on 403 */
#define MSR_PMM 2 /* Performance monitor mark on POWER */
#define MSR_RI 1 /* Recoverable interrupt */
#define MSR_LE 0 /* Little-endian mode */
#define MSR_LE 0 /* Little-endian mode hflags */
#define msr_sf env->msr[MSR_SF]
#define msr_isf env->msr[MSR_ISF]
#define msr_hv env->msr[MSR_HV]
#define msr_ucle env->msr[MSR_UCLE]
#define msr_vr env->msr[MSR_VR]
#define msr_spe env->msr[MSR_SPE]
#define msr_ap env->msr[MSR_AP]
#define msr_sa env->msr[MSR_SA]
#define msr_key env->msr[MSR_KEY]
@ -436,6 +590,7 @@ struct ppc_tlb_t {
#define msr_fe0 env->msr[MSR_FE0]
#define msr_se env->msr[MSR_SE]
#define msr_dwe env->msr[MSR_DWE]
#define msr_uble env->msr[MSR_UBLE]
#define msr_be env->msr[MSR_BE]
#define msr_de env->msr[MSR_DE]
#define msr_fe1 env->msr[MSR_FE1]
@ -465,7 +620,7 @@ struct CPUPPCState {
target_ulong t0, t1, t2;
#endif
/* general purpose registers */
target_ulong gpr[32];
ppc_gpr_t gpr[32];
/* LR */
target_ulong lr;
/* CTR */
@ -482,7 +637,7 @@ struct CPUPPCState {
/* machine state register */
uint8_t msr[64];
/* temporary general purpose registers */
target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */
ppc_gpr_t tgpr[4]; /* Used to speed-up TLB assist handlers */
/* Floating point execution context */
/* temporary float registers */
@ -529,9 +684,12 @@ struct CPUPPCState {
ppc_dcr_t *dcr_env;
/* PowerPC TLB registers (for 4xx and 60x software driven TLBs) */
int nb_tlb;
int nb_ways, last_way;
ppc_tlb_t tlb[128];
int nb_tlb; /* Total number of TLB */
int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
int nb_ways; /* Number of ways in the TLB set */
int last_way; /* Last used way used to allocate TLB in a LRU way */
int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */
ppc_tlb_t *tlb; /* TLB is optional. Allocate them only if needed */
/* Callbacks for specific checks on some implementations */
int (*tlb_check_more)(CPUPPCState *env, struct ppc_tlb_t *tlb, int *prot,
target_ulong vaddr, int rw, int acc_type,
@ -568,6 +726,16 @@ struct CPUPPCState {
int (*osi_call)(struct CPUPPCState *env);
};
/* Context used internally during MMU translations */
typedef struct mmu_ctx_t mmu_ctx_t;
struct mmu_ctx_t {
target_phys_addr_t raddr; /* Real address */
int prot; /* Protection bits */
target_phys_addr_t pg_addr[2]; /* PTE tables base addresses */
target_ulong ptem; /* Virtual segment ID | API */
int key; /* Access key */
};
/*****************************************************************************/
CPUPPCState *cpu_ppc_init(void);
int cpu_ppc_exec(CPUPPCState *s);
@ -583,6 +751,7 @@ void cpu_loop_exit(void);
void dump_stack (CPUPPCState *env);
#if !defined(CONFIG_USER_ONLY)
target_ulong do_load_ibatu (CPUPPCState *env, int nr);
target_ulong do_load_ibatl (CPUPPCState *env, int nr);
void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value);
@ -591,23 +760,17 @@ target_ulong do_load_dbatu (CPUPPCState *env, int nr);
target_ulong do_load_dbatl (CPUPPCState *env, int nr);
void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value);
void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value);
target_ulong do_load_nip (CPUPPCState *env);
void do_store_nip (CPUPPCState *env, target_ulong value);
target_ulong do_load_sdr1 (CPUPPCState *env);
void do_store_sdr1 (CPUPPCState *env, target_ulong value);
target_ulong do_load_asr (CPUPPCState *env);
void do_store_asr (CPUPPCState *env, target_ulong value);
target_ulong do_load_sr (CPUPPCState *env, int srnum);
void do_store_sr (CPUPPCState *env, int srnum, target_ulong value);
uint32_t do_load_cr (CPUPPCState *env);
void do_store_cr (CPUPPCState *env, uint32_t value, uint32_t mask);
uint32_t do_load_xer (CPUPPCState *env);
void do_store_xer (CPUPPCState *env, uint32_t value);
#endif
uint32_t ppc_load_xer (CPUPPCState *env);
void ppc_store_xer (CPUPPCState *env, uint32_t value);
target_ulong do_load_msr (CPUPPCState *env);
void do_store_msr (CPUPPCState *env, target_ulong value);
float64 do_load_fpscr (CPUPPCState *env);
void do_store_fpscr (CPUPPCState *env, float64 f, uint32_t mask);
void do_compute_hflags (CPUPPCState *env);
@ -660,13 +823,13 @@ void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
#define SPR_SDR1 (0x019)
#define SPR_SRR0 (0x01A)
#define SPR_SRR1 (0x01B)
#define SPR_440_PID (0x030)
#define SPR_440_DECAR (0x036)
#define SPR_BOOKE_PID (0x030)
#define SPR_BOOKE_DECAR (0x036)
#define SPR_CSRR0 (0x03A)
#define SPR_CSRR1 (0x03B)
#define SPR_440_DEAR (0x03D)
#define SPR_440_ESR (0x03E)
#define SPR_440_IVPR (0x03F)
#define SPR_BOOKE_DEAR (0x03D)
#define SPR_BOOKE_ESR (0x03E)
#define SPR_BOOKE_EVPR (0x03F)
#define SPR_8xx_EIE (0x050)
#define SPR_8xx_EID (0x051)
#define SPR_8xx_NRE (0x052)
@ -709,59 +872,70 @@ void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
#define SPR_TBL (0x11C)
#define SPR_TBU (0x11D)
#define SPR_SVR (0x11E)
#define SPR_440_PIR (0x11E)
#define SPR_BOOKE_PIR (0x11E)
#define SPR_PVR (0x11F)
#define SPR_HSPRG0 (0x130)
#define SPR_440_DBSR (0x130)
#define SPR_BOOKE_DBSR (0x130)
#define SPR_HSPRG1 (0x131)
#define SPR_440_DBCR0 (0x134)
#define SPR_BOOKE_DBCR0 (0x134)
#define SPR_IBCR (0x135)
#define SPR_440_DBCR1 (0x135)
#define SPR_BOOKE_DBCR1 (0x135)
#define SPR_DBCR (0x136)
#define SPR_HDEC (0x136)
#define SPR_440_DBCR2 (0x136)
#define SPR_BOOKE_DBCR2 (0x136)
#define SPR_HIOR (0x137)
#define SPR_MBAR (0x137)
#define SPR_RMOR (0x138)
#define SPR_440_IAC1 (0x138)
#define SPR_BOOKE_IAC1 (0x138)
#define SPR_HRMOR (0x139)
#define SPR_440_IAC2 (0x139)
#define SPR_BOOKE_IAC2 (0x139)
#define SPR_HSSR0 (0x13A)
#define SPR_440_IAC3 (0x13A)
#define SPR_BOOKE_IAC3 (0x13A)
#define SPR_HSSR1 (0x13B)
#define SPR_440_IAC4 (0x13B)
#define SPR_BOOKE_IAC4 (0x13B)
#define SPR_LPCR (0x13C)
#define SPR_440_DAC1 (0x13C)
#define SPR_BOOKE_DAC1 (0x13C)
#define SPR_LPIDR (0x13D)
#define SPR_DABR2 (0x13D)
#define SPR_440_DAC2 (0x13D)
#define SPR_440_DVC1 (0x13E)
#define SPR_440_DVC2 (0x13F)
#define SPR_440_TSR (0x150)
#define SPR_440_TCR (0x154)
#define SPR_440_IVOR0 (0x190)
#define SPR_440_IVOR1 (0x191)
#define SPR_440_IVOR2 (0x192)
#define SPR_440_IVOR3 (0x193)
#define SPR_440_IVOR4 (0x194)
#define SPR_440_IVOR5 (0x195)
#define SPR_440_IVOR6 (0x196)
#define SPR_440_IVOR7 (0x197)
#define SPR_440_IVOR8 (0x198)
#define SPR_440_IVOR9 (0x199)
#define SPR_440_IVOR10 (0x19A)
#define SPR_440_IVOR11 (0x19B)
#define SPR_440_IVOR12 (0x19C)
#define SPR_440_IVOR13 (0x19D)
#define SPR_440_IVOR14 (0x19E)
#define SPR_440_IVOR15 (0x19F)
#define SPR_BOOKE_DAC2 (0x13D)
#define SPR_BOOKE_DVC1 (0x13E)
#define SPR_BOOKE_DVC2 (0x13F)
#define SPR_BOOKE_TSR (0x150)
#define SPR_BOOKE_TCR (0x154)
#define SPR_BOOKE_IVOR0 (0x190)
#define SPR_BOOKE_IVOR1 (0x191)
#define SPR_BOOKE_IVOR2 (0x192)
#define SPR_BOOKE_IVOR3 (0x193)
#define SPR_BOOKE_IVOR4 (0x194)
#define SPR_BOOKE_IVOR5 (0x195)
#define SPR_BOOKE_IVOR6 (0x196)
#define SPR_BOOKE_IVOR7 (0x197)
#define SPR_BOOKE_IVOR8 (0x198)
#define SPR_BOOKE_IVOR9 (0x199)
#define SPR_BOOKE_IVOR10 (0x19A)
#define SPR_BOOKE_IVOR11 (0x19B)
#define SPR_BOOKE_IVOR12 (0x19C)
#define SPR_BOOKE_IVOR13 (0x19D)
#define SPR_BOOKE_IVOR14 (0x19E)
#define SPR_BOOKE_IVOR15 (0x19F)
#define SPR_E500_SPEFSCR (0x200)
#define SPR_E500_BBEAR (0x201)
#define SPR_E500_BBTAR (0x202)
#define SPR_BOOKE_ATBL (0x20E)
#define SPR_BOOKE_ATBU (0x20F)
#define SPR_IBAT0U (0x210)
#define SPR_E500_IVOR32 (0x210)
#define SPR_IBAT0L (0x211)
#define SPR_E500_IVOR33 (0x211)
#define SPR_IBAT1U (0x212)
#define SPR_E500_IVOR34 (0x212)
#define SPR_IBAT1L (0x213)
#define SPR_E500_IVOR35 (0x213)
#define SPR_IBAT2U (0x214)
#define SPR_IBAT2L (0x215)
#define SPR_E500_L1CFG0 (0x215)
#define SPR_IBAT3U (0x216)
#define SPR_E500_L1CFG1 (0x216)
#define SPR_IBAT3L (0x217)
#define SPR_DBAT0U (0x218)
#define SPR_DBAT0L (0x219)
@ -782,11 +956,25 @@ void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
#define SPR_DBAT4U (0x238)
#define SPR_DBAT4L (0x239)
#define SPR_DBAT5U (0x23A)
#define SPR_E500_MCSRR0 (0x23A)
#define SPR_DBAT5L (0x23B)
#define SPR_E500_MCSRR1 (0x23B)
#define SPR_DBAT6U (0x23C)
#define SPR_E500_MCSR (0x23C)
#define SPR_DBAT6L (0x23D)
#define SPR_E500_MCAR (0x23D)
#define SPR_DBAT7U (0x23E)
#define SPR_DBAT7L (0x23F)
#define SPR_E500_MAS0 (0x270)
#define SPR_E500_MAS1 (0x271)
#define SPR_E500_MAS2 (0x272)
#define SPR_E500_MAS3 (0x273)
#define SPR_E500_MAS4 (0x274)
#define SPR_E500_MAS6 (0x276)
#define SPR_E500_PID1 (0x279)
#define SPR_E500_PID2 (0x27A)
#define SPR_E500_TLB0CFG (0x2B0)
#define SPR_E500_TLB1CFG (0x2B1)
#define SPR_440_INV0 (0x370)
#define SPR_440_INV1 (0x371)
#define SPR_440_INV2 (0x372)
@ -819,6 +1007,7 @@ void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
#define SPR_UPMC4 (0x3AE)
#define SPR_USDA (0x3AF)
#define SPR_40x_ZPR (0x3B0)
#define SPR_E500_MAS7 (0x3B0)
#define SPR_40x_PID (0x3B1)
#define SPR_440_MMUCR (0x3B2)
#define SPR_4xx_CCR0 (0x3B3)
@ -843,8 +1032,8 @@ void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
#define SPR_403_VTBU (0x3CD)
#define SPR_DMISS (0x3D0)
#define SPR_DCMP (0x3D1)
#define SPR_DHASH1 (0x3D2)
#define SPR_DHASH2 (0x3D3)
#define SPR_HASH1 (0x3D2)
#define SPR_HASH2 (0x3D3)
#define SPR_4xx_ICDBDR (0x3D3)
#define SPR_IMISS (0x3D4)
#define SPR_40x_ESR (0x3D4)
@ -871,15 +1060,20 @@ void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
#define SPR_IABR (0x3F2)
#define SPR_40x_DBCR0 (0x3F2)
#define SPR_601_HID2 (0x3F2)
#define SPR_E500_L1CSR0 (0x3F2)
#define SPR_HID2 (0x3F3)
#define SPR_E500_L1CSR1 (0x3F3)
#define SPR_440_DBDR (0x3F3)
#define SPR_40x_IAC1 (0x3F4)
#define SPR_E500_MMUCSR0 (0x3F4)
#define SPR_DABR (0x3F5)
#define DABR_MASK (~(target_ulong)0x7)
#define SPR_E500_BUCSR (0x3F5)
#define SPR_40x_IAC2 (0x3F5)
#define SPR_601_HID5 (0x3F5)
#define SPR_40x_DAC1 (0x3F6)
#define SPR_40x_DAC2 (0x3F7)
#define SPR_E500_MMUCFG (0x3F7)
#define SPR_L2PM (0x3F8)
#define SPR_750_HID2 (0x3F8)
#define SPR_L2CR (0x3F9)
@ -899,7 +1093,9 @@ void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
#define SPR_PIR (0x3FF)
#define SPR_403_PBU2 (0x3FF)
#define SPR_601_HID15 (0x3FF)
#define SPR_E500_SVR (0x3FF)
/*****************************************************************************/
/* Memory access type :
* may be needed for precise access rights control and precise exceptions.
*/

78
target-ppc/exec.h
View file

@ -1,7 +1,7 @@
/*
* PowerPC emulation definitions for qemu.
*
* Copyright (c) 2003-2005 Jocelyn Mayer
* Copyright (c) 2003-2007 Jocelyn Mayer
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
@ -24,15 +24,34 @@
#include "dyngen-exec.h"
#define TARGET_LONG_BITS 32
#include "cpu.h"
#include "exec-all.h"
register struct CPUPPCState *env asm(AREG0);
register uint32_t T0 asm(AREG1);
register uint32_t T1 asm(AREG2);
register uint32_t T2 asm(AREG3);
#if TARGET_LONG_BITS > HOST_LONG_BITS
/* no registers can be used */
#define T0 (env->t0)
#define T1 (env->t1)
#define T2 (env->t2)
#else
/* This may be more efficient if HOST_LONG_BITS > TARGET_LONG_BITS
* To be set to one when we'll be sure it does not cause bugs....
*/
#if 0
register unsigned long T0 asm(AREG1);
register unsigned long T1 asm(AREG2);
register unsigned long T2 asm(AREG3);
#else
register target_ulong T0 asm(AREG1);
register target_ulong T1 asm(AREG2);
register target_ulong T2 asm(AREG3);
#endif
#endif
/* XXX: to clean: remove this mess */
#define PARAM(n) ((uint32_t)PARAM##n)
#define SPARAM(n) ((int32_t)PARAM##n)
#define FT0 (env->ft0)
#define FT1 (env->ft1)
#define FT2 (env->ft2)
@ -43,14 +62,28 @@ register uint32_t T2 asm(AREG3);
# define RETURN() __asm__ __volatile__("" : : : "memory");
#endif
#include "cpu.h"
#include "exec-all.h"
static inline uint32_t rotl (uint32_t i, int n)
static inline target_ulong rotl8 (target_ulong i, int n)
{
return ((i << n) | (i >> (32 - n)));
return (((uint8_t)i << n) | ((uint8_t)i >> (8 - n)));
}
static inline target_ulong rotl16 (target_ulong i, int n)
{
return (((uint16_t)i << n) | ((uint16_t)i >> (16 - n)));
}
static inline target_ulong rotl32 (target_ulong i, int n)
{
return (((uint32_t)i << n) | ((uint32_t)i >> (32 - n)));
}
#if defined(TARGET_PPC64)
static inline target_ulong rotl64 (target_ulong i, int n)
{
return (((uint64_t)i << n) | ((uint64_t)i >> (64 - n)));
}
#endif
#if !defined(CONFIG_USER_ONLY)
#include "softmmu_exec.h"
#endif /* !defined(CONFIG_USER_ONLY) */
@ -58,23 +91,14 @@ static inline uint32_t rotl (uint32_t i, int n)
void do_raise_exception_err (uint32_t exception, int error_code);
void do_raise_exception (uint32_t exception);
void do_sraw(void);
int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong vaddr,
int rw, int access_type, int check_BATs);
void do_fctiw (void);
void do_fctiwz (void);
void do_fnmadd (void);
void do_fnmsub (void);
void do_fsqrt (void);
void do_fres (void);
void do_frsqrte (void);
void do_fsel (void);
void do_fcmpu (void);
void do_fcmpo (void);
void do_check_reservation (void);
void do_icbi (void);
void do_tlbia (void);
void do_tlbie (void);
void ppc6xx_tlb_invalidate_all (CPUState *env);
void ppc6xx_tlb_invalidate_virt (CPUState *env, target_ulong eaddr,
int is_code);
void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code,
target_ulong pte0, target_ulong pte1);
static inline void env_to_regs(void)
{
@ -84,7 +108,7 @@ static inline void regs_to_env(void)
{
}
int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw,
int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
int is_user, int is_softmmu);
#endif /* !defined (__PPC_H__) */

911
target-ppc/helper.c
View file

File diff suppressed because it is too large Load diff

79
target-ppc/mfrom_table.c Normal file
View file

@ -0,0 +1,79 @@
static const uint8_t mfrom_ROM_table[602] =
{
77, 77, 76, 76, 75, 75, 74, 74,
73, 73, 72, 72, 71, 71, 70, 70,
69, 69, 68, 68, 68, 67, 67, 66,
66, 65, 65, 64, 64, 64, 63, 63,
62, 62, 61, 61, 61, 60, 60, 59,
59, 58, 58, 58, 57, 57, 56, 56,
56, 55, 55, 54, 54, 54, 53, 53,
53, 52, 52, 51, 51, 51, 50, 50,
50, 49, 49, 49, 48, 48, 47, 47,
47, 46, 46, 46, 45, 45, 45, 44,
44, 44, 43, 43, 43, 42, 42, 42,
42, 41, 41, 41, 40, 40, 40, 39,
39, 39, 39, 38, 38, 38, 37, 37,
37, 37, 36, 36, 36, 35, 35, 35,
35, 34, 34, 34, 34, 33, 33, 33,
33, 32, 32, 32, 32, 31, 31, 31,
31, 30, 30, 30, 30, 29, 29, 29,
29, 28, 28, 28, 28, 28, 27, 27,
27, 27, 26, 26, 26, 26, 26, 25,
25, 25, 25, 25, 24, 24, 24, 24,
24, 23, 23, 23, 23, 23, 23, 22,
22, 22, 22, 22, 21, 21, 21, 21,
21, 21, 20, 20, 20, 20, 20, 20,
19, 19, 19, 19, 19, 19, 19, 18,
18, 18, 18, 18, 18, 17, 17, 17,
17, 17, 17, 17, 16, 16, 16, 16,
16, 16, 16, 16, 15, 15, 15, 15,
15, 15, 15, 15, 14, 14, 14, 14,
14, 14, 14, 14, 13, 13, 13, 13,
13, 13, 13, 13, 13, 12, 12, 12,
12, 12, 12, 12, 12, 12, 12, 11,
11, 11, 11, 11, 11, 11, 11, 11,
11, 11, 10, 10, 10, 10, 10, 10,
10, 10, 10, 10, 10, 9, 9, 9,
9, 9, 9, 9, 9, 9, 9, 9,
9, 9, 8, 8, 8, 8, 8, 8,
8, 8, 8, 8, 8, 8, 8, 8,
7, 7, 7, 7, 7, 7, 7, 7,
7, 7, 7, 7, 7, 7, 7, 7,
7, 6, 6, 6, 6, 6, 6, 6,
6, 6, 6, 6, 6, 6, 6, 6,
6, 6, 6, 6, 5, 5, 5, 5,
5, 5, 5, 5, 5, 5, 5, 5,
5, 5, 5, 5, 5, 5, 5, 5,
5, 5, 5, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 3,
3, 3, 3, 3, 3, 3, 3, 3,
3, 3, 3, 3, 3, 3, 3, 3,
3, 3, 3, 3, 3, 3, 3, 3,
3, 3, 3, 3, 3, 3, 3, 3,
3, 3, 3, 3, 3, 2, 2, 2,
2, 2, 2, 2, 2, 2, 2, 2,
2, 2, 2, 2, 2, 2, 2, 2,
2, 2, 2, 2, 2, 2, 2, 2,
2, 2, 2, 2, 2, 2, 2, 2,
2, 2, 2, 2, 2, 2, 2, 2,
2, 2, 2, 2, 2, 2, 2, 2,
2, 2, 2, 2, 2, 2, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 0,
};

33
target-ppc/mfrom_table_gen.c Normal file
View file

@ -0,0 +1,33 @@
#define _GNU_SOURCE
#include <stdint.h>
#include <stdio.h>
#include <math.h>
int main (void)
{
double d;
uint8_t n;
int i;
printf("static const uint8_t mfrom_ROM_table[602] =\n{\n ");
for (i = 0; i < 602; i++) {
/* Extremly decomposed:
* -T0 / 256
* T0 = 256 * log10(10 + 1.0) + 0.5
*/
d = -i;
d /= 256.0;
d = exp10(d);
d += 1.0;
d = log10(d);
d *= 256;
d += 0.5;
n = d;
printf("%3d, ", n);
if ((i & 7) == 7)
printf("\n ");
}
printf("\n};\n");
return 0;
}

904
target-ppc/op.c
View file

File diff suppressed because it is too large Load diff

676
target-ppc/op_helper.c
View file

@ -1,7 +1,7 @@
/*
* PowerPC emulation helpers for qemu.
*
* Copyright (c) 2003-2005 Jocelyn Mayer
* Copyright (c) 2003-2007 Jocelyn Mayer
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
@ -30,6 +30,7 @@
//#define DEBUG_OP
//#define DEBUG_EXCEPTIONS
//#define DEBUG_SOFTWARE_TLB
//#define FLUSH_ALL_TLBS
#define Ts0 (long)((target_long)T0)
@ -38,7 +39,7 @@
/*****************************************************************************/
/* Exceptions processing helpers */
void cpu_loop_exit(void)
void cpu_loop_exit (void)
{
longjmp(env->jmp_env, 1);
}
@ -55,17 +56,130 @@ void do_raise_exception_err (uint32_t exception, int error_code)
break;
default:
break;
}
}
env->exception_index = exception;
env->error_code = error_code;
cpu_loop_exit();
}
}
void do_raise_exception (uint32_t exception)
{
do_raise_exception_err(exception, 0);
}
/*****************************************************************************/
/* Registers load and stores */
void do_load_cr (void)
{
T0 = (env->crf[0] << 28) |
(env->crf[1] << 24) |
(env->crf[2] << 20) |
(env->crf[3] << 16) |
(env->crf[4] << 12) |
(env->crf[5] << 8) |
(env->crf[6] << 4) |
(env->crf[7] << 0);
}
void do_store_cr (uint32_t mask)
{
int i, sh;
for (i = 0, sh = 7; i < 8; i++, sh --) {
if (mask & (1 << sh))
env->crf[i] = (T0 >> (sh * 4)) & 0xFUL;
}
}
void do_load_xer (void)
{
T0 = (xer_so << XER_SO) |
(xer_ov << XER_OV) |
(xer_ca << XER_CA) |
(xer_bc << XER_BC) |
(xer_cmp << XER_CMP);
}
void do_store_xer (void)
{
xer_so = (T0 >> XER_SO) & 0x01;
xer_ov = (T0 >> XER_OV) & 0x01;
xer_ca = (T0 >> XER_CA) & 0x01;
xer_cmp = (T0 >> XER_CMP) & 0xFF;
xer_bc = (T0 >> XER_BC) & 0x3F;
}
void do_load_fpscr (void)
{
/* The 32 MSB of the target fpr are undefined.
* They'll be zero...
*/
union {
float64 d;
struct {
uint32_t u[2];
} s;
} u;
int i;
#ifdef WORDS_BIGENDIAN
#define WORD0 0
#define WORD1 1
#else
#define WORD0 1
#define WORD1 0
#endif
u.s.u[WORD0] = 0;
u.s.u[WORD1] = 0;
for (i = 0; i < 8; i++)
u.s.u[WORD1] |= env->fpscr[i] << (4 * i);
FT0 = u.d;
}
void do_store_fpscr (uint32_t mask)
{
/*
* We use only the 32 LSB of the incoming fpr
*/
union {
double d;
struct {
uint32_t u[2];
} s;
} u;
int i, rnd_type;
u.d = FT0;
if (mask & 0x80)
env->fpscr[0] = (env->fpscr[0] & 0x9) | ((u.s.u[WORD1] >> 28) & ~0x9);
for (i = 1; i < 7; i++) {
if (mask & (1 << (7 - i)))
env->fpscr[i] = (u.s.u[WORD1] >> (4 * (7 - i))) & 0xF;
}
/* TODO: update FEX & VX */
/* Set rounding mode */
switch (env->fpscr[0] & 0x3) {
case 0:
/* Best approximation (round to nearest) */
rnd_type = float_round_nearest_even;
break;
case 1:
/* Smaller magnitude (round toward zero) */
rnd_type = float_round_to_zero;
break;
case 2:
/* Round toward +infinite */
rnd_type = float_round_up;
break;
default:
case 3:
/* Round toward -infinite */
rnd_type = float_round_down;
break;
}
set_float_rounding_mode(rnd_type, &env->fp_status);
}
/*****************************************************************************/
/* Fixed point operations helpers */
void do_addo (void)
@ -381,7 +495,7 @@ void do_fres (void)
} p;
if (likely(isnormal(FT0))) {
FT0 = (float)(1.0 / FT0);
FT0 = float32_div(1.0, FT0, &env->fp_status);
} else {
p.d = FT0;
if (p.i == 0x8000000000000000ULL) {
@ -467,8 +581,8 @@ void do_fcmpo (void)
} else {
T0 = 0x01UL;
env->fpscr[4] |= 0x1;
/* I don't know how to test "quiet" nan... */
if (0 /* || ! quiet_nan(...) */) {
if (!float64_is_signaling_nan(FT0) || !float64_is_signaling_nan(FT1)) {
/* Quiet NaN case */
env->fpscr[6] |= 0x1;
if (!(env->fpscr[1] & 0x8))
env->fpscr[4] |= 0x8;
@ -479,6 +593,7 @@ void do_fcmpo (void)
env->fpscr[3] = T0;
}
#if !defined (CONFIG_USER_ONLY)
void do_rfi (void)
{
env->nip = env->spr[SPR_SRR0] & ~0x00000003;
@ -489,14 +604,15 @@ void do_rfi (void)
#endif
env->interrupt_request |= CPU_INTERRUPT_EXITTB;
}
#endif
void do_tw (uint32_t cmp, int flags)
void do_tw (int flags)
{
if (!likely(!((Ts0 < (int32_t)cmp && (flags & 0x10)) ||
(Ts0 > (int32_t)cmp && (flags & 0x08)) ||
(Ts0 == (int32_t)cmp && (flags & 0x04)) ||
(T0 < cmp && (flags & 0x02)) ||
(T0 > cmp && (flags & 0x01)))))
if (!likely(!((Ts0 < Ts1 && (flags & 0x10)) ||
(Ts0 > Ts1 && (flags & 0x08)) ||
(Ts0 == Ts1 && (flags & 0x04)) ||
(T0 < T1 && (flags & 0x02)) ||
(T0 > T1 && (flags & 0x01)))))
do_raise_exception_err(EXCP_PROGRAM, EXCP_TRAP);
}
@ -519,22 +635,313 @@ void do_icbi (void)
}
/*****************************************************************************/
/* MMU related helpers */
/* TLB invalidation helpers */
void do_tlbia (void)
/* PowerPC 601 specific instructions (POWER bridge) */
void do_POWER_abso (void)
{
tlb_flush(env, 1);
if (T0 == INT32_MIN) {
T0 = INT32_MAX;
xer_ov = 1;
xer_so = 1;
} else {
T0 = -T0;
xer_ov = 0;
}
}
void do_tlbie (void)
void do_POWER_clcs (void)
{
#if !defined(FLUSH_ALL_TLBS)
tlb_flush_page(env, T0);
#else
do_tlbia();
switch (T0) {
case 0x0CUL:
/* Instruction cache line size */
T0 = ICACHE_LINE_SIZE;
break;
case 0x0DUL:
/* Data cache line size */
T0 = DCACHE_LINE_SIZE;
break;
case 0x0EUL:
/* Minimum cache line size */
T0 = ICACHE_LINE_SIZE < DCACHE_LINE_SIZE ?
ICACHE_LINE_SIZE : DCACHE_LINE_SIZE;
break;
case 0x0FUL:
/* Maximum cache line size */
T0 = ICACHE_LINE_SIZE > DCACHE_LINE_SIZE ?
ICACHE_LINE_SIZE : DCACHE_LINE_SIZE;
break;
default:
/* Undefined */
break;
}
}
void do_POWER_div (void)
{
uint64_t tmp;
if ((Ts0 == INT32_MIN && Ts1 == -1) || Ts1 == 0) {
T0 = (long)((-1) * (T0 >> 31));
env->spr[SPR_MQ] = 0;
} else {
tmp = ((uint64_t)T0 << 32) | env->spr[SPR_MQ];
env->spr[SPR_MQ] = tmp % T1;
T0 = tmp / Ts1;
}
}
void do_POWER_divo (void)
{
int64_t tmp;
if ((Ts0 == INT32_MIN && Ts1 == -1) || Ts1 == 0) {
T0 = (long)((-1) * (T0 >> 31));
env->spr[SPR_MQ] = 0;
xer_ov = 1;
xer_so = 1;
} else {
tmp = ((uint64_t)T0 << 32) | env->spr[SPR_MQ];
env->spr[SPR_MQ] = tmp % T1;
tmp /= Ts1;
if (tmp > (int64_t)INT32_MAX || tmp < (int64_t)INT32_MIN) {
xer_ov = 1;
xer_so = 1;
} else {
xer_ov = 0;
}
T0 = tmp;
}
}
void do_POWER_divs (void)
{
if ((Ts0 == INT32_MIN && Ts1 == -1) || Ts1 == 0) {
T0 = (long)((-1) * (T0 >> 31));
env->spr[SPR_MQ] = 0;
} else {
env->spr[SPR_MQ] = T0 % T1;
T0 = Ts0 / Ts1;
}
}
void do_POWER_divso (void)
{
if ((Ts0 == INT32_MIN && Ts1 == -1) || Ts1 == 0) {
T0 = (long)((-1) * (T0 >> 31));
env->spr[SPR_MQ] = 0;
xer_ov = 1;
xer_so = 1;
} else {
T0 = Ts0 / Ts1;
env->spr[SPR_MQ] = Ts0 % Ts1;
xer_ov = 0;
}
}
void do_POWER_dozo (void)
{
if (Ts1 > Ts0) {
T2 = T0;
T0 = T1 - T0;
if (((~T2) ^ T1 ^ (-1)) & ((~T2) ^ T0) & (1 << 31)) {
xer_so = 1;
xer_ov = 1;
} else {
xer_ov = 0;
}
} else {
T0 = 0;
xer_ov = 0;
}
}
void do_POWER_maskg (void)
{
uint32_t ret;
if (T0 == T1 + 1) {
ret = -1;
} else {
ret = (((uint32_t)(-1)) >> (T0)) ^
(((uint32_t)(-1) >> (T1)) >> 1);
if (T0 > T1)
ret = ~ret;
}
T0 = ret;
}
void do_POWER_mulo (void)
{
uint64_t tmp;
tmp = (uint64_t)T0 * (uint64_t)T1;
env->spr[SPR_MQ] = tmp >> 32;
T0 = tmp;
if (tmp >> 32 != ((uint64_t)T0 >> 16) * ((uint64_t)T1 >> 16)) {
xer_ov = 1;
xer_so = 1;
} else {
xer_ov = 0;
}
}
#if !defined (CONFIG_USER_ONLY)
void do_POWER_rac (void)
{
#if 0
mmu_ctx_t ctx;
/* We don't have to generate many instances of this instruction,
* as rac is supervisor only.
*/
if (get_physical_address(env, &ctx, T0, 0, ACCESS_INT, 1) == 0)
T0 = ctx.raddr;
#endif
}
void do_POWER_rfsvc (void)
{
env->nip = env->lr & ~0x00000003UL;
T0 = env->ctr & 0x0000FFFFUL;
do_store_msr(env, T0);
#if defined (DEBUG_OP)
dump_rfi();
#endif
env->interrupt_request |= CPU_INTERRUPT_EXITTB;
}
/* PowerPC 601 BAT management helper */
void do_store_601_batu (int nr)
{
do_store_ibatu(env, nr, T0);
env->DBAT[0][nr] = env->IBAT[0][nr];
env->DBAT[1][nr] = env->IBAT[1][nr];
}
#endif
/*****************************************************************************/
/* 602 specific instructions */
/* mfrom is the most crazy instruction ever seen, imho ! */
/* Real implementation uses a ROM table. Do the same */
#define USE_MFROM_ROM_TABLE
void do_op_602_mfrom (void)
{
if (likely(T0 < 602)) {
#ifdef USE_MFROM_ROM_TABLE
#include "mfrom_table.c"
T0 = mfrom_ROM_table[T0];
#else
double d;
/* Extremly decomposed:
* -T0 / 256
* T0 = 256 * log10(10 + 1.0) + 0.5
*/
d = T0;
d = float64_div(d, 256, &env->fp_status);
d = float64_chs(d);
d = exp10(d); // XXX: use float emulation function
d = float64_add(d, 1.0, &env->fp_status);
d = log10(d); // XXX: use float emulation function
d = float64_mul(d, 256, &env->fp_status);
d = float64_add(d, 0.5, &env->fp_status);
T0 = float64_round_to_int(d, &env->fp_status);
#endif
} else {
T0 = 0;
}
}
/*****************************************************************************/
/* Embedded PowerPC specific helpers */
void do_405_check_ov (void)
{
if (likely(((T1 ^ T2) >> 31) || !((T0 ^ T2) >> 31))) {
xer_ov = 0;
} else {
xer_ov = 1;
xer_so = 1;
}
}
void do_405_check_sat (void)
{
if (!likely(((T1 ^ T2) >> 31) || !((T0 ^ T2) >> 31))) {
/* Saturate result */
if (T2 >> 31) {
T0 = INT32_MIN;
} else {
T0 = INT32_MAX;
}
}
}
#if !defined(CONFIG_USER_ONLY)
void do_4xx_rfci (void)
{
env->nip = env->spr[SPR_40x_SRR2];
T0 = env->spr[SPR_40x_SRR3] & ~0xFFFF0000;
do_store_msr(env, T0);
#if defined (DEBUG_OP)
dump_rfi();
#endif
env->interrupt_request = CPU_INTERRUPT_EXITTB;
}
void do_4xx_load_dcr (int dcrn)
{
target_ulong val;
if (unlikely(env->dcr_read == NULL))
do_raise_exception_err(EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_INVAL);
else if (unlikely((*env->dcr_read)(env->dcr_env, dcrn, &val) != 0))
do_raise_exception_err(EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_REG);
else
T0 = val;
}
void do_4xx_store_dcr (int dcrn)
{
if (unlikely(env->dcr_write == NULL))
do_raise_exception_err(EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_INVAL);
else if (unlikely((*env->dcr_write)(env->dcr_env, dcrn, T0) != 0))
do_raise_exception_err(EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_REG);
}
void do_load_403_pb (int num)
{
T0 = env->pb[num];
}
void do_store_403_pb (int num)
{
if (likely(env->pb[num] != T0)) {
env->pb[num] = T0;
/* Should be optimized */
tlb_flush(env, 1);
}
}
#endif
/* 440 specific */
void do_440_dlmzb (void)
{
target_ulong mask;
int i;
i = 1;
for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
if ((T0 & mask) == 0)
goto done;
i++;
}
for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
if ((T1 & mask) == 0)
break;
i++;
}
done:
T0 = i;
}
/*****************************************************************************/
/* Softmmu support */
#if !defined (CONFIG_USER_ONLY)
@ -570,7 +977,7 @@ void tlb_fill (target_ulong addr, int is_write, int is_user, void *retaddr)
saved_env = env;
env = cpu_single_env;
ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, is_user, 1);
if (!likely(ret == 0)) {
if (unlikely(ret != 0)) {
if (likely(retaddr)) {
/* now we have a real cpu fault */
pc = (target_phys_addr_t)retaddr;
@ -579,11 +986,230 @@ void tlb_fill (target_ulong addr, int is_write, int is_user, void *retaddr)
/* the PC is inside the translated code. It means that we have
a virtual CPU fault */
cpu_restore_state(tb, env, pc, NULL);
}
}
}
do_raise_exception_err(env->exception_index, env->error_code);
}
env = saved_env;
}
#endif /* !CONFIG_USER_ONLY */
/* TLB invalidation helpers */
void do_tlbia (void)
{
if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_6xx)) {
ppc6xx_tlb_invalidate_all(env);
} else if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_4xx)) {
/* XXX: TODO */
#if 0
ppcbooke_tlb_invalidate_all(env);
#endif
} else {
tlb_flush(env, 1);
}
}
void do_tlbie (void)
{
#if !defined(FLUSH_ALL_TLBS)
if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_6xx)) {
ppc6xx_tlb_invalidate_virt(env, T0 & TARGET_PAGE_MASK, 0);
if (env->id_tlbs == 1)
ppc6xx_tlb_invalidate_virt(env, T0 & TARGET_PAGE_MASK, 1);
} else if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_4xx)) {
/* XXX: TODO */
#if 0
ppcbooke_tlb_invalidate_virt(env, T0 & TARGET_PAGE_MASK,
env->spr[SPR_BOOKE_PID]);
#endif
} else {
/* tlbie invalidate TLBs for all segments */
T0 &= TARGET_PAGE_MASK;
T0 &= ~((target_ulong)-1 << 28);
/* XXX: this case should be optimized,
* giving a mask to tlb_flush_page
*/
tlb_flush_page(env, T0 | (0x0 << 28));
tlb_flush_page(env, T0 | (0x1 << 28));
tlb_flush_page(env, T0 | (0x2 << 28));
tlb_flush_page(env, T0 | (0x3 << 28));
tlb_flush_page(env, T0 | (0x4 << 28));
tlb_flush_page(env, T0 | (0x5 << 28));
tlb_flush_page(env, T0 | (0x6 << 28));
tlb_flush_page(env, T0 | (0x7 << 28));
tlb_flush_page(env, T0 | (0x8 << 28));
tlb_flush_page(env, T0 | (0x9 << 28));
tlb_flush_page(env, T0 | (0xA << 28));
tlb_flush_page(env, T0 | (0xB << 28));
tlb_flush_page(env, T0 | (0xC << 28));
tlb_flush_page(env, T0 | (0xD << 28));
tlb_flush_page(env, T0 | (0xE << 28));
tlb_flush_page(env, T0 | (0xF << 28));
}
#else
do_tlbia();
#endif
}
/* Software driven TLBs management */
/* PowerPC 602/603 software TLB load instructions helpers */
void do_load_6xx_tlb (int is_code)
{
target_ulong RPN, CMP, EPN;
int way;
RPN = env->spr[SPR_RPA];
if (is_code) {
CMP = env->spr[SPR_ICMP];
EPN = env->spr[SPR_IMISS];
} else {
CMP = env->spr[SPR_DCMP];
EPN = env->spr[SPR_DMISS];
}
way = (env->spr[SPR_SRR1] >> 17) & 1;
#if defined (DEBUG_SOFTWARE_TLB)
if (loglevel != 0) {
fprintf(logfile, "%s: EPN %08lx %08lx PTE0 %08lx PTE1 %08lx way %d\n",
__func__, (unsigned long)T0, (unsigned long)EPN,
(unsigned long)CMP, (unsigned long)RPN, way);
}
#endif
/* Store this TLB */
ppc6xx_tlb_store(env, T0 & TARGET_PAGE_MASK, way, is_code, CMP, RPN);
}
/* Helpers for 4xx TLB management */
void do_4xx_tlbia (void)
{
#if 0
ppc_tlb_t *tlb;
target_ulong page, end;
int i;
for (i = 0; i < 64; i++) {
tlb = &env->tlb[i];
if (tlb->prot & PAGE_VALID) {
end = tlb->EPN + tlb->size;
for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
tlb_flush_page(env, page);
tlb->prot &= ~PAGE_VALID;
}
}
#endif
}
void do_4xx_tlbre_lo (void)
{
#if 0
ppc_tlb_t *tlb;
T0 &= 0x3F;
tlb = &env->tlb[T0];
T0 = tlb->stor[0];
env->spr[SPR_40x_PID] = tlb->pid;
#endif
}
void do_4xx_tlbre_hi (void)
{
#if 0
ppc_tlb_t *tlb;
T0 &= 0x3F;
tlb = &env->tlb[T0];
T0 = tlb->stor[1];
#endif
}
static int tlb_4xx_search (target_ulong virtual)
{
#if 0
ppc_tlb_t *tlb;
target_ulong base, mask;
int i, ret;
/* Default return value is no match */
ret = -1;
for (i = 0; i < 64; i++) {
tlb = &env->tlb[i];
/* Check TLB validity */
if (!(tlb->prot & PAGE_VALID))
continue;
/* Check TLB PID vs current PID */
if (tlb->pid != 0 && tlb->pid != env->spr[SPR_40x_PID])
continue;
/* Check TLB address vs virtual address */
base = tlb->EPN;
mask = ~(tlb->size - 1);
if ((base & mask) != (virtual & mask))
continue;
ret = i;
break;
}
return ret;
#else
return -1;
#endif
}
void do_4xx_tlbsx (void)
{
T0 = tlb_4xx_search(T0);
}
void do_4xx_tlbsx_ (void)
{
int tmp = xer_ov;
T0 = tlb_4xx_search(T0);
if (T0 != -1)
tmp |= 0x02;
env->crf[0] = tmp;
}
void do_4xx_tlbwe_lo (void)
{
#if 0
ppc_tlb_t *tlb;
target_ulong page, end;
T0 &= 0x3F;
tlb = &env->tlb[T0];
/* Invalidate previous TLB (if it's valid) */
if (tlb->prot & PAGE_VALID) {
end = tlb->EPN + tlb->size;
for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
tlb_flush_page(env, page);
}
tlb->size = 1024 << (2 * ((T1 >> 7) & 0x7));
tlb->EPN = (T1 & 0xFFFFFC00) & ~(tlb->size - 1);
if (T1 & 0x400)
tlb->prot |= PAGE_VALID;
else
tlb->prot &= ~PAGE_VALID;
tlb->pid = env->spr[SPR_BOOKE_PID]; /* PID */
/* Invalidate new TLB (if valid) */
if (tlb->prot & PAGE_VALID) {
end = tlb->EPN + tlb->size;
for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
tlb_flush_page(env, page);
}
#endif
}
void do_4xx_tlbwe_hi (void)
{
#if 0
ppc_tlb_t *tlb;
T0 &= 0x3F;
tlb = &env->tlb[T0];
tlb->RPN = T1 & 0xFFFFFC00;
tlb->prot = PAGE_READ;
if (T1 & 0x200)
tlb->prot |= PAGE_EXEC;
if (T1 & 0x100)
tlb->prot |= PAGE_WRITE;
#endif
}
#endif /* !CONFIG_USER_ONLY */

132
target-ppc/op_helper.h Normal file
View file

@ -0,0 +1,132 @@
/*
* PowerPC emulation helpers header for qemu.
*
* Copyright (c) 2003-2007 Jocelyn Mayer
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#if defined(MEMSUFFIX)
/* Memory load/store helpers */
void glue(do_lsw, MEMSUFFIX) (int dst);
void glue(do_lsw_le, MEMSUFFIX) (int dst);
void glue(do_stsw, MEMSUFFIX) (int src);
void glue(do_stsw_le, MEMSUFFIX) (int src);
void glue(do_lmw, MEMSUFFIX) (int dst);
void glue(do_lmw_le, MEMSUFFIX) (int dst);
void glue(do_stmw, MEMSUFFIX) (int src);
void glue(do_stmw_le, MEMSUFFIX) (int src);
void glue(do_POWER_lscbx, MEMSUFFIX) (int dest, int ra, int rb);
void glue(do_POWER2_lfq, MEMSUFFIX) (void);
void glue(do_POWER2_lfq_le, MEMSUFFIX) (void);
void glue(do_POWER2_stfq, MEMSUFFIX) (void);
void glue(do_POWER2_stfq_le, MEMSUFFIX) (void);
#else
/* Registers load and stores */
void do_load_cr (void);
void do_store_cr (uint32_t mask);
void do_load_xer (void);
void do_store_xer (void);
void do_load_fpscr (void);
void do_store_fpscr (uint32_t mask);
/* Integer arithmetic helpers */
void do_addo (void);
void do_addco (void);
void do_adde (void);
void do_addeo (void);
void do_addmeo (void);
void do_addzeo (void);
void do_divwo (void);
void do_divwuo (void);
void do_mullwo (void);
void do_nego (void);
void do_subfo (void);
void do_subfco (void);
void do_subfe (void);
void do_subfeo (void);
void do_subfmeo (void);
void do_subfzeo (void);
void do_sraw(void);
/* Floating-point arithmetic helpers */
void do_fsqrt (void);
void do_fres (void);
void do_frsqrte (void);
void do_fsel (void);
void do_fnmadd (void);
void do_fnmsub (void);
void do_fctiw (void);
void do_fctiwz (void);
void do_fcmpu (void);
void do_fcmpo (void);
void do_tw (int flags);
void do_icbi (void);
#if !defined(CONFIG_USER_ONLY)
void do_rfi (void);
void do_tlbia (void);
void do_tlbie (void);
void do_load_6xx_tlb (int is_code);
#endif
/* POWER / PowerPC 601 specific helpers */
void do_store_601_batu (int nr);
void do_POWER_abso (void);
void do_POWER_clcs (void);
void do_POWER_div (void);
void do_POWER_divo (void);
void do_POWER_divs (void);
void do_POWER_divso (void);
void do_POWER_dozo (void);
void do_POWER_maskg (void);
void do_POWER_mulo (void);
#if !defined(CONFIG_USER_ONLY)
void do_POWER_rac (void);
void do_POWER_rfsvc (void);
#endif
/* PowerPC 602 specific helper */
#if !defined(CONFIG_USER_ONLY)
void do_op_602_mfrom (void);
#endif
/* PowerPC 4xx specific helpers */
void do_405_check_ov (void);
void do_405_check_sat (void);
#if !defined(CONFIG_USER_ONLY)
void do_4xx_load_dcr (int dcrn);
void do_4xx_store_dcr (int dcrn);
void do_4xx_rfci (void);
void do_4xx_tlbre_lo (void);
void do_4xx_tlbre_hi (void);
void do_4xx_tlbsx (void);
void do_4xx_tlbsx_ (void);
void do_4xx_tlbwe_lo (void);
void do_4xx_tlbwe_hi (void);
#endif
void do_440_dlmzb (void);
#if !defined(CONFIG_USER_ONLY)
void do_load_403_pb (int num);
void do_store_403_pb (int num);
#endif
#endif

206
target-ppc/op_helper_mem.h
View file

@ -1,20 +1,78 @@
/*
* PowerPC emulation micro-operations helpers for qemu.
*
* Copyright (c) 2003-2007 Jocelyn Mayer
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
/* Multiple word / string load and store */
static inline target_ulong glue(ld32r, MEMSUFFIX) (target_ulong EA)
{
uint32_t tmp = glue(ldl, MEMSUFFIX)(EA);
return ((tmp & 0xFF000000UL) >> 24) | ((tmp & 0x00FF0000UL) >> 8) |
((tmp & 0x0000FF00UL) << 8) | ((tmp & 0x000000FFUL) << 24);
}
static inline void glue(st32r, MEMSUFFIX) (target_ulong EA, target_ulong data)
{
uint32_t tmp =
((data & 0xFF000000UL) >> 24) | ((data & 0x00FF0000UL) >> 8) |
((data & 0x0000FF00UL) << 8) | ((data & 0x000000FFUL) << 24);
glue(stl, MEMSUFFIX)(EA, tmp);
}
void glue(do_lmw, MEMSUFFIX) (int dst)
{
for (; dst < 32; dst++, T0 += 4) {
ugpr(dst) = glue(ldl, MEMSUFFIX)(T0);
}
}
void glue(do_stmw, MEMSUFFIX) (int src)
{
for (; src < 32; src++, T0 += 4) {
glue(stl, MEMSUFFIX)(T0, ugpr(src));
}
}
void glue(do_lmw_le, MEMSUFFIX) (int dst)
{
for (; dst < 32; dst++, T0 += 4) {
ugpr(dst) = glue(ld32r, MEMSUFFIX)(T0);
}
}
void glue(do_stmw_le, MEMSUFFIX) (int src)
{
for (; src < 32; src++, T0 += 4) {
glue(st32r, MEMSUFFIX)(T0, ugpr(src));
}
}
void glue(do_lsw, MEMSUFFIX) (int dst)
{
uint32_t tmp;
int sh;
#if 0
if (loglevel > 0) {
fprintf(logfile, "%s: addr=0x%08x count=%d reg=%d\n",
__func__, T0, T1, dst);
}
#endif
for (; T1 > 3; T1 -= 4, T0 += 4) {
ugpr(dst++) = glue(ldl, MEMSUFFIX)(T0);
if (dst == 32)
if (unlikely(dst == 32))
dst = 0;
}
if (T1 > 0) {
if (unlikely(T1 != 0)) {
tmp = 0;
for (sh = 24; T1 > 0; T1--, T0++, sh -= 8) {
tmp |= glue(ldub, MEMSUFFIX)(T0) << sh;
@ -27,18 +85,12 @@ void glue(do_stsw, MEMSUFFIX) (int src)
{
int sh;
#if 0
if (loglevel > 0) {
fprintf(logfile, "%s: addr=0x%08x count=%d reg=%d\n",
__func__, T0, T1, src);
}
#endif
for (; T1 > 3; T1 -= 4, T0 += 4) {
glue(stl, MEMSUFFIX)(T0, ugpr(src++));
if (src == 32)
if (unlikely(src == 32))
src = 0;
}
if (T1 > 0) {
if (unlikely(T1 != 0)) {
for (sh = 24; T1 > 0; T1--, T0++, sh -= 8)
glue(stb, MEMSUFFIX)(T0, (ugpr(src) >> sh) & 0xFF);
}
@ -49,20 +101,12 @@ void glue(do_lsw_le, MEMSUFFIX) (int dst)
uint32_t tmp;
int sh;
#if 0
if (loglevel > 0) {
fprintf(logfile, "%s: addr=0x%08x count=%d reg=%d\n",
__func__, T0, T1, dst);
}
#endif
for (; T1 > 3; T1 -= 4, T0 += 4) {
tmp = glue(ldl, MEMSUFFIX)(T0);
ugpr(dst++) = ((tmp & 0xFF000000) >> 24) | ((tmp & 0x00FF0000) >> 8) |
((tmp & 0x0000FF00) << 8) | ((tmp & 0x000000FF) << 24);
if (dst == 32)
ugpr(dst++) = glue(ld32r, MEMSUFFIX)(T0);
if (unlikely(dst == 32))
dst = 0;
}
if (T1 > 0) {
if (unlikely(T1 != 0)) {
tmp = 0;
for (sh = 0; T1 > 0; T1--, T0++, sh += 8) {
tmp |= glue(ldub, MEMSUFFIX)(T0) << sh;
@ -73,28 +117,108 @@ void glue(do_lsw_le, MEMSUFFIX) (int dst)
void glue(do_stsw_le, MEMSUFFIX) (int src)
{
uint32_t tmp;
int sh;
#if 0
if (loglevel > 0) {
fprintf(logfile, "%s: addr=0x%08x count=%d reg=%d\n",
__func__, T0, T1, src);
}
#endif
for (; T1 > 3; T1 -= 4, T0 += 4) {
tmp = ((ugpr(src++) & 0xFF000000) >> 24);
tmp |= ((ugpr(src++) & 0x00FF0000) >> 8);
tmp |= ((ugpr(src++) & 0x0000FF00) << 8);
tmp |= ((ugpr(src++) & 0x000000FF) << 24);
glue(stl, MEMSUFFIX)(T0, tmp);
if (src == 32)
glue(st32r, MEMSUFFIX)(T0, ugpr(src++));
if (unlikely(src == 32))
src = 0;
}
if (T1 > 0) {
if (unlikely(T1 != 0)) {
for (sh = 0; T1 > 0; T1--, T0++, sh += 8)
glue(stb, MEMSUFFIX)(T0, (ugpr(src) >> sh) & 0xFF);
}
}
/* PPC 601 specific instructions (POWER bridge) */
// XXX: to be tested
void glue(do_POWER_lscbx, MEMSUFFIX) (int dest, int ra, int rb)
{
int i, c, d, reg;
d = 24;
reg = dest;
for (i = 0; i < T1; i++) {
c = glue(ldub, MEMSUFFIX)(T0++);
/* ra (if not 0) and rb are never modified */
if (likely(reg != rb && (ra == 0 || reg != ra))) {
ugpr(reg) = (ugpr(reg) & ~(0xFF << d)) | (c << d);
}
if (unlikely(c == T2))
break;
if (likely(d != 0)) {
d -= 8;
} else {
d = 24;
reg++;
reg = reg & 0x1F;
}
}
T0 = i;
}
/* XXX: TAGs are not managed */
void glue(do_POWER2_lfq, MEMSUFFIX) (void)
{
FT0 = glue(ldfq, MEMSUFFIX)(T0);
FT1 = glue(ldfq, MEMSUFFIX)(T0 + 4);
}
static inline double glue(ldfqr, MEMSUFFIX) (target_ulong EA)
{
union {
double d;
uint64_t u;
} u;
u.d = glue(ldfq, MEMSUFFIX)(EA);
u.u = ((u.u & 0xFF00000000000000ULL) >> 56) |
((u.u & 0x00FF000000000000ULL) >> 40) |
((u.u & 0x0000FF0000000000ULL) >> 24) |
((u.u & 0x000000FF00000000ULL) >> 8) |
((u.u & 0x00000000FF000000ULL) << 8) |
((u.u & 0x0000000000FF0000ULL) << 24) |
((u.u & 0x000000000000FF00ULL) << 40) |
((u.u & 0x00000000000000FFULL) << 56);
return u.d;
}
void glue(do_POWER2_lfq_le, MEMSUFFIX) (void)
{
FT0 = glue(ldfqr, MEMSUFFIX)(T0 + 4);
FT1 = glue(ldfqr, MEMSUFFIX)(T0);
}
void glue(do_POWER2_stfq, MEMSUFFIX) (void)
{
glue(stfq, MEMSUFFIX)(T0, FT0);
glue(stfq, MEMSUFFIX)(T0 + 4, FT1);
}
static inline void glue(stfqr, MEMSUFFIX) (target_ulong EA, double d)
{
union {
double d;
uint64_t u;
} u;
u.d = d;
u.u = ((u.u & 0xFF00000000000000ULL) >> 56) |
((u.u & 0x00FF000000000000ULL) >> 40) |
((u.u & 0x0000FF0000000000ULL) >> 24) |
((u.u & 0x000000FF00000000ULL) >> 8) |
((u.u & 0x00000000FF000000ULL) << 8) |
((u.u & 0x0000000000FF0000ULL) << 24) |
((u.u & 0x000000000000FF00ULL) << 40) |
((u.u & 0x00000000000000FFULL) << 56);
glue(stfq, MEMSUFFIX)(EA, u.d);
}
void glue(do_POWER2_stfq_le, MEMSUFFIX) (void)
{
glue(stfqr, MEMSUFFIX)(T0 + 4, FT0);
glue(stfqr, MEMSUFFIX)(T0, FT1);
}
#undef MEMSUFFIX

138
target-ppc/op_mem.h
View file

@ -1,6 +1,22 @@
/* External helpers */
void glue(do_lsw, MEMSUFFIX) (int dst);
void glue(do_stsw, MEMSUFFIX) (int src);
/*
* PowerPC emulation micro-operations for qemu.
*
* Copyright (c) 2003-2007 Jocelyn Mayer
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
static inline uint16_t glue(ld16r, MEMSUFFIX) (target_ulong EA)
{
@ -11,7 +27,7 @@ static inline uint16_t glue(ld16r, MEMSUFFIX) (target_ulong EA)
static inline int32_t glue(ld16rs, MEMSUFFIX) (target_ulong EA)
{
int16_t tmp = glue(lduw, MEMSUFFIX)(EA);
return ((tmp & 0xFF00) >> 8) | ((tmp & 0x00FF) << 8);
return (int16_t)((tmp & 0xFF00) >> 8) | ((tmp & 0x00FF) << 8);
}
static inline uint32_t glue(ld32r, MEMSUFFIX) (target_ulong EA)
@ -80,41 +96,25 @@ PPC_ST_OP(wbr_le, stl);
/*** Integer load and store multiple ***/
PPC_OP(glue(lmw, MEMSUFFIX))
{
int dst = PARAM(1);
for (; dst < 32; dst++, T0 += 4) {
ugpr(dst) = glue(ldl, MEMSUFFIX)(T0);
}
RETURN();
}
PPC_OP(glue(stmw, MEMSUFFIX))
{
int src = PARAM(1);
for (; src < 32; src++, T0 += 4) {
glue(stl, MEMSUFFIX)(T0, ugpr(src));
}
glue(do_lmw, MEMSUFFIX)(PARAM1);
RETURN();
}
PPC_OP(glue(lmw_le, MEMSUFFIX))
{
int dst = PARAM(1);
glue(do_lmw_le, MEMSUFFIX)(PARAM1);
RETURN();
}
for (; dst < 32; dst++, T0 += 4) {
ugpr(dst) = glue(ld32r, MEMSUFFIX)(T0);
}
PPC_OP(glue(stmw, MEMSUFFIX))
{
glue(do_stmw, MEMSUFFIX)(PARAM1);
RETURN();
}
PPC_OP(glue(stmw_le, MEMSUFFIX))
{
int src = PARAM(1);
for (; src < 32; src++, T0 += 4) {
glue(st32r, MEMSUFFIX)(T0, ugpr(src));
}
glue(do_stmw_le, MEMSUFFIX)(PARAM1);
RETURN();
}
@ -125,7 +125,6 @@ PPC_OP(glue(lswi, MEMSUFFIX))
RETURN();
}
void glue(do_lsw_le, MEMSUFFIX) (int dst);
PPC_OP(glue(lswi_le, MEMSUFFIX))
{
glue(do_lsw_le, MEMSUFFIX)(PARAM(1));
@ -139,9 +138,9 @@ PPC_OP(glue(lswi_le, MEMSUFFIX))
*/
PPC_OP(glue(lswx, MEMSUFFIX))
{
if (T1 > 0) {
if ((PARAM(1) < PARAM(2) && (PARAM(1) + T1) > PARAM(2)) ||
(PARAM(1) < PARAM(3) && (PARAM(1) + T1) > PARAM(3))) {
if (unlikely(T1 > 0)) {
if (unlikely((PARAM1 < PARAM2 && (PARAM1 + T1) > PARAM2) ||
(PARAM1 < PARAM3 && (PARAM1 + T1) > PARAM3))) {
do_raise_exception_err(EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_LSWX);
} else {
glue(do_lsw, MEMSUFFIX)(PARAM(1));
@ -152,9 +151,9 @@ PPC_OP(glue(lswx, MEMSUFFIX))
PPC_OP(glue(lswx_le, MEMSUFFIX))
{
if (T1 > 0) {
if ((PARAM(1) < PARAM(2) && (PARAM(1) + T1) > PARAM(2)) ||
(PARAM(1) < PARAM(3) && (PARAM(1) + T1) > PARAM(3))) {
if (unlikely(T1 > 0)) {
if (unlikely((PARAM1 < PARAM2 && (PARAM1 + T1) > PARAM2) ||
(PARAM1 < PARAM3 && (PARAM1 + T1) > PARAM3))) {
do_raise_exception_err(EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_LSWX);
} else {
glue(do_lsw_le, MEMSUFFIX)(PARAM(1));
@ -169,7 +168,6 @@ PPC_OP(glue(stsw, MEMSUFFIX))
RETURN();
}
void glue(do_stsw_le, MEMSUFFIX) (int src);
PPC_OP(glue(stsw_le, MEMSUFFIX))
{
glue(do_stsw_le, MEMSUFFIX)(PARAM(1));
@ -180,7 +178,7 @@ PPC_OP(glue(stsw_le, MEMSUFFIX))
#define PPC_STF_OP(name, op) \
PPC_OP(glue(glue(st, name), MEMSUFFIX)) \
{ \
glue(op, MEMSUFFIX)(T0, FT1); \
glue(op, MEMSUFFIX)(T0, FT0); \
RETURN(); \
}
@ -228,7 +226,7 @@ PPC_STF_OP(fs_le, stflr);
#define PPC_LDF_OP(name, op) \
PPC_OP(glue(glue(l, name), MEMSUFFIX)) \
{ \
FT1 = glue(op, MEMSUFFIX)(T0); \
FT0 = glue(op, MEMSUFFIX)(T0); \
RETURN(); \
}
@ -277,7 +275,7 @@ PPC_LDF_OP(fs_le, ldflr);
/* Load and set reservation */
PPC_OP(glue(lwarx, MEMSUFFIX))
{
if (T0 & 0x03) {
if (unlikely(T0 & 0x03)) {
do_raise_exception(EXCP_ALIGN);
} else {
T1 = glue(ldl, MEMSUFFIX)(T0);
@ -288,7 +286,7 @@ PPC_OP(glue(lwarx, MEMSUFFIX))
PPC_OP(glue(lwarx_le, MEMSUFFIX))
{
if (T0 & 0x03) {
if (unlikely(T0 & 0x03)) {
do_raise_exception(EXCP_ALIGN);
} else {
T1 = glue(ld32r, MEMSUFFIX)(T0);
@ -300,33 +298,33 @@ PPC_OP(glue(lwarx_le, MEMSUFFIX))
/* Store with reservation */
PPC_OP(glue(stwcx, MEMSUFFIX))
{
if (T0 & 0x03) {
if (unlikely(T0 & 0x03)) {
do_raise_exception(EXCP_ALIGN);
} else {
if (regs->reserve != T0) {
if (unlikely(regs->reserve != T0)) {
env->crf[0] = xer_ov;
} else {
glue(stl, MEMSUFFIX)(T0, T1);
env->crf[0] = xer_ov | 0x02;
}
}
regs->reserve = 0;
regs->reserve = -1;
RETURN();
}
PPC_OP(glue(stwcx_le, MEMSUFFIX))
{
if (T0 & 0x03) {
if (unlikely(T0 & 0x03)) {
do_raise_exception(EXCP_ALIGN);
} else {
if (regs->reserve != T0) {
if (unlikely(regs->reserve != T0)) {
env->crf[0] = xer_ov;
} else {
glue(st32r, MEMSUFFIX)(T0, T1);
env->crf[0] = xer_ov | 0x02;
}
}
regs->reserve = 0;
regs->reserve = -1;
RETURN();
}
@ -340,6 +338,17 @@ PPC_OP(glue(dcbz, MEMSUFFIX))
glue(stl, MEMSUFFIX)(T0 + 0x14, 0);
glue(stl, MEMSUFFIX)(T0 + 0x18, 0);
glue(stl, MEMSUFFIX)(T0 + 0x1C, 0);
#if DCACHE_LINE_SIZE == 64
/* XXX: cache line size should be 64 for POWER & PowerPC 601 */
glue(stl, MEMSUFFIX)(T0 + 0x20UL, 0);
glue(stl, MEMSUFFIX)(T0 + 0x24UL, 0);
glue(stl, MEMSUFFIX)(T0 + 0x28UL, 0);
glue(stl, MEMSUFFIX)(T0 + 0x2CUL, 0);
glue(stl, MEMSUFFIX)(T0 + 0x30UL, 0);
glue(stl, MEMSUFFIX)(T0 + 0x34UL, 0);
glue(stl, MEMSUFFIX)(T0 + 0x38UL, 0);
glue(stl, MEMSUFFIX)(T0 + 0x3CUL, 0);
#endif
RETURN();
}
@ -368,4 +377,41 @@ PPC_OP(glue(ecowx_le, MEMSUFFIX))
RETURN();
}
/* XXX: those micro-ops need tests ! */
/* PowerPC 601 specific instructions (POWER bridge) */
void OPPROTO glue(op_POWER_lscbx, MEMSUFFIX) (void)
{
/* When byte count is 0, do nothing */
if (likely(T1 > 0)) {
glue(do_POWER_lscbx, MEMSUFFIX)(PARAM1, PARAM2, PARAM3);
}
RETURN();
}
/* POWER2 quad load and store */
/* XXX: TAGs are not managed */
void OPPROTO glue(op_POWER2_lfq, MEMSUFFIX) (void)
{
glue(do_POWER2_lfq, MEMSUFFIX)();
RETURN();
}
void glue(op_POWER2_lfq_le, MEMSUFFIX) (void)
{
glue(do_POWER2_lfq_le, MEMSUFFIX)();
RETURN();
}
void OPPROTO glue(op_POWER2_stfq, MEMSUFFIX) (void)
{
glue(do_POWER2_stfq, MEMSUFFIX)();
RETURN();
}
void OPPROTO glue(op_POWER2_stfq_le, MEMSUFFIX) (void)
{
glue(do_POWER2_stfq_le, MEMSUFFIX)();
RETURN();
}
#undef MEMSUFFIX

73
target-ppc/op_template.h
View file

@ -1,7 +1,7 @@
/*
* PowerPC emulation micro-operations for qemu.
*
* Copyright (c) 2003-2005 Jocelyn Mayer
* Copyright (c) 2003-2007 Jocelyn Mayer
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
@ -19,107 +19,97 @@
*/
/* General purpose registers moves */
void OPPROTO glue(op_load_gpr_T0_gpr, REG)(void)
void OPPROTO glue(op_load_gpr_T0_gpr, REG) (void)
{
T0 = regs->gpr[REG];
RETURN();
}
void OPPROTO glue(op_load_gpr_T1_gpr, REG)(void)
void OPPROTO glue(op_load_gpr_T1_gpr, REG) (void)
{
T1 = regs->gpr[REG];
RETURN();
}
void OPPROTO glue(op_load_gpr_T2_gpr, REG)(void)
void OPPROTO glue(op_load_gpr_T2_gpr, REG) (void)
{
T2 = regs->gpr[REG];
RETURN();
}
void OPPROTO glue(op_store_T0_gpr_gpr, REG)(void)
void OPPROTO glue(op_store_T0_gpr_gpr, REG) (void)
{
regs->gpr[REG] = T0;
RETURN();
}
void OPPROTO glue(op_store_T1_gpr_gpr, REG)(void)
void OPPROTO glue(op_store_T1_gpr_gpr, REG) (void)
{
regs->gpr[REG] = T1;
RETURN();
}
void OPPROTO glue(op_store_T2_gpr_gpr, REG)(void)
#if 0 // unused
void OPPROTO glue(op_store_T2_gpr_gpr, REG) (void)
{
regs->gpr[REG] = T2;
RETURN();
}
#endif
#if REG <= 7
/* Condition register moves */
void OPPROTO glue(op_load_crf_T0_crf, REG)(void)
void OPPROTO glue(op_load_crf_T0_crf, REG) (void)
{
T0 = regs->crf[REG];
RETURN();
}
void OPPROTO glue(op_load_crf_T1_crf, REG)(void)
void OPPROTO glue(op_load_crf_T1_crf, REG) (void)
{
T1 = regs->crf[REG];
RETURN();
}
void OPPROTO glue(op_store_T0_crf_crf, REG)(void)
void OPPROTO glue(op_store_T0_crf_crf, REG) (void)
{
regs->crf[REG] = T0;
RETURN();
}
void OPPROTO glue(op_store_T1_crf_crf, REG)(void)
void OPPROTO glue(op_store_T1_crf_crf, REG) (void)
{
regs->crf[REG] = T1;
RETURN();
}
/* Floating point condition and status register moves */
void OPPROTO glue(op_load_fpscr_T0_fpscr, REG)(void)
void OPPROTO glue(op_load_fpscr_T0_fpscr, REG) (void)
{
T0 = regs->fpscr[REG];
RETURN();
}
#if REG == 0
void OPPROTO glue(op_store_T0_fpscr_fpscr, REG)(void)
void OPPROTO glue(op_store_T0_fpscr_fpscr, REG) (void)
{
regs->fpscr[REG] = (regs->fpscr[REG] & 0x9) | (T0 & ~0x9);
RETURN();
}
void OPPROTO glue(op_store_T0_fpscri_fpscr, REG)(void)
{
regs->fpscr[REG] = (regs->fpscr[REG] & ~0x9) | (PARAM(1) & 0x9);
RETURN();
}
void OPPROTO glue(op_clear_fpscr_fpscr, REG)(void)
void OPPROTO glue(op_clear_fpscr_fpscr, REG) (void)
{
regs->fpscr[REG] = (regs->fpscr[REG] & 0x9);
RETURN();
}
#else
void OPPROTO glue(op_store_T0_fpscr_fpscr, REG)(void)
void OPPROTO glue(op_store_T0_fpscr_fpscr, REG) (void)
{
regs->fpscr[REG] = T0;
RETURN();
}
void OPPROTO glue(op_store_T0_fpscri_fpscr, REG)(void)
{
regs->fpscr[REG] = PARAM(1);
RETURN();
}
void OPPROTO glue(op_clear_fpscr_fpscr, REG)(void)
void OPPROTO glue(op_clear_fpscr_fpscr, REG) (void)
{
regs->fpscr[REG] = 0x0;
RETURN();
@ -129,55 +119,42 @@ void OPPROTO glue(op_clear_fpscr_fpscr, REG)(void)
#endif /* REG <= 7 */
/* floating point registers moves */
void OPPROTO glue(op_load_fpr_FT0_fpr, REG)(void)
void OPPROTO glue(op_load_fpr_FT0_fpr, REG) (void)
{
FT0 = env->fpr[REG];
RETURN();
}
void OPPROTO glue(op_store_FT0_fpr_fpr, REG)(void)
void OPPROTO glue(op_store_FT0_fpr_fpr, REG) (void)
{
env->fpr[REG] = FT0;
RETURN();
}
void OPPROTO glue(op_load_fpr_FT1_fpr, REG)(void)
void OPPROTO glue(op_load_fpr_FT1_fpr, REG) (void)
{
FT1 = env->fpr[REG];
RETURN();
}
void OPPROTO glue(op_store_FT1_fpr_fpr, REG)(void)
void OPPROTO glue(op_store_FT1_fpr_fpr, REG) (void)
{
env->fpr[REG] = FT1;
RETURN();
}
void OPPROTO glue(op_load_fpr_FT2_fpr, REG)(void)
void OPPROTO glue(op_load_fpr_FT2_fpr, REG) (void)
{
FT2 = env->fpr[REG];
RETURN();
}
void OPPROTO glue(op_store_FT2_fpr_fpr, REG)(void)
#if 0 // unused
void OPPROTO glue(op_store_FT2_fpr_fpr, REG) (void)
{
env->fpr[REG] = FT2;
RETURN();
}
#if REG <= 15
/* Segment register moves */
void OPPROTO glue(op_load_sr, REG)(void)
{
T0 = env->sr[REG];
RETURN();
}
void OPPROTO glue(op_store_sr, REG)(void)
{
do_store_sr(env, REG, T0);
RETURN();
}
#endif
#undef REG

2124
target-ppc/translate.c
View file

File diff suppressed because it is too large Load diff

1918
target-ppc/translate_init.c
View file

File diff suppressed because it is too large Load diff