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hw/arm/fsl-imx8mp: Add I2C controllers

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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-id: 20250223114708.1780-11-shentey@gmail.com
[PMM: drop static const from i2c_table for GCC 7.5]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Bernhard Beschow 2025-02-23 12:47:00 +01:00 • committed by Peter Maydell
parent a17c1d932e
commit 764f18afb2
4 changed files with 43 additions and 0 deletions
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1
docs/system/arm/imx8mp-evk.rst
View file

@ -15,6 +15,7 @@ The ``imx8mp-evk`` machine implements the following devices:
* 3 USDHC Storage Controllers * 3 USDHC Storage Controllers
* 1 Designware PCI Express Controller * 1 Designware PCI Express Controller
* 5 GPIO Controllers * 5 GPIO Controllers
* 6 I2C Controllers
* Secure Non-Volatile Storage (SNVS) including an RTC * Secure Non-Volatile Storage (SNVS) including an RTC
* Clock Tree * Clock Tree

2
hw/arm/Kconfig
View file

@ -595,11 +595,13 @@ config FSL_IMX7
config FSL_IMX8MP config FSL_IMX8MP
bool bool
imply I2C_DEVICES
imply PCI_DEVICES imply PCI_DEVICES
select ARM_GIC select ARM_GIC
select FSL_IMX8MP_ANALOG select FSL_IMX8MP_ANALOG
select FSL_IMX8MP_CCM select FSL_IMX8MP_CCM
select IMX select IMX
select IMX_I2C
select PCI_EXPRESS_DESIGNWARE select PCI_EXPRESS_DESIGNWARE
select PCI_EXPRESS_FSL_IMX8M_PHY select PCI_EXPRESS_FSL_IMX8M_PHY
select SDHCI select SDHCI

29
hw/arm/fsl-imx8mp.c
View file

@ -208,6 +208,11 @@ static void fsl_imx8mp_init(Object *obj)
object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL); object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL);
} }
for (i = 0; i < FSL_IMX8MP_NUM_I2CS; i++) {
g_autofree char *name = g_strdup_printf("i2c%d", i + 1);
object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C);
}
for (i = 0; i < FSL_IMX8MP_NUM_GPIOS; i++) { for (i = 0; i < FSL_IMX8MP_NUM_GPIOS; i++) {
g_autofree char *name = g_strdup_printf("gpio%d", i + 1); g_autofree char *name = g_strdup_printf("gpio%d", i + 1);
object_initialize_child(obj, name, &s->gpio[i], TYPE_IMX_GPIO); object_initialize_child(obj, name, &s->gpio[i], TYPE_IMX_GPIO);
@ -360,6 +365,29 @@ static void fsl_imx8mp_realize(DeviceState *dev, Error **errp)
qdev_get_gpio_in(gicdev, serial_table[i].irq)); qdev_get_gpio_in(gicdev, serial_table[i].irq));
} }
/* I2Cs */
for (i = 0; i < FSL_IMX8MP_NUM_I2CS; i++) {
struct {
hwaddr addr;
unsigned int irq;
} i2c_table[FSL_IMX8MP_NUM_I2CS] = {
{ fsl_imx8mp_memmap[FSL_IMX8MP_I2C1].addr, FSL_IMX8MP_I2C1_IRQ },
{ fsl_imx8mp_memmap[FSL_IMX8MP_I2C2].addr, FSL_IMX8MP_I2C2_IRQ },
{ fsl_imx8mp_memmap[FSL_IMX8MP_I2C3].addr, FSL_IMX8MP_I2C3_IRQ },
{ fsl_imx8mp_memmap[FSL_IMX8MP_I2C4].addr, FSL_IMX8MP_I2C4_IRQ },
{ fsl_imx8mp_memmap[FSL_IMX8MP_I2C5].addr, FSL_IMX8MP_I2C5_IRQ },
{ fsl_imx8mp_memmap[FSL_IMX8MP_I2C6].addr, FSL_IMX8MP_I2C6_IRQ },
};
if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c[i]), errp)) {
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
qdev_get_gpio_in(gicdev, i2c_table[i].irq));
}
/* GPIOs */ /* GPIOs */
for (i = 0; i < FSL_IMX8MP_NUM_GPIOS; i++) { for (i = 0; i < FSL_IMX8MP_NUM_GPIOS; i++) {
struct { struct {
@ -470,6 +498,7 @@ static void fsl_imx8mp_realize(DeviceState *dev, Error **errp)
case FSL_IMX8MP_GIC_DIST: case FSL_IMX8MP_GIC_DIST:
case FSL_IMX8MP_GIC_REDIST: case FSL_IMX8MP_GIC_REDIST:
case FSL_IMX8MP_GPIO1 ... FSL_IMX8MP_GPIO5: case FSL_IMX8MP_GPIO1 ... FSL_IMX8MP_GPIO5:
case FSL_IMX8MP_I2C1 ... FSL_IMX8MP_I2C6:
case FSL_IMX8MP_PCIE1: case FSL_IMX8MP_PCIE1:
case FSL_IMX8MP_PCIE_PHY1: case FSL_IMX8MP_PCIE_PHY1:
case FSL_IMX8MP_RAM: case FSL_IMX8MP_RAM:

11
include/hw/arm/fsl-imx8mp.h
View file

@ -12,6 +12,7 @@
#include "cpu.h" #include "cpu.h"
#include "hw/char/imx_serial.h" #include "hw/char/imx_serial.h"
#include "hw/gpio/imx_gpio.h" #include "hw/gpio/imx_gpio.h"
#include "hw/i2c/imx_i2c.h"
#include "hw/intc/arm_gicv3_common.h" #include "hw/intc/arm_gicv3_common.h"
#include "hw/misc/imx7_snvs.h" #include "hw/misc/imx7_snvs.h"
#include "hw/misc/imx8mp_analog.h" #include "hw/misc/imx8mp_analog.h"
@ -31,6 +32,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(FslImx8mpState, FSL_IMX8MP)
enum FslImx8mpConfiguration { enum FslImx8mpConfiguration {
FSL_IMX8MP_NUM_CPUS = 4, FSL_IMX8MP_NUM_CPUS = 4,
FSL_IMX8MP_NUM_GPIOS = 5, FSL_IMX8MP_NUM_GPIOS = 5,
FSL_IMX8MP_NUM_I2CS = 6,
FSL_IMX8MP_NUM_IRQS = 160, FSL_IMX8MP_NUM_IRQS = 160,
FSL_IMX8MP_NUM_UARTS = 4, FSL_IMX8MP_NUM_UARTS = 4,
FSL_IMX8MP_NUM_USDHCS = 3, FSL_IMX8MP_NUM_USDHCS = 3,
@ -45,6 +47,7 @@ struct FslImx8mpState {
IMX8MPCCMState ccm; IMX8MPCCMState ccm;
IMX8MPAnalogState analog; IMX8MPAnalogState analog;
IMX7SNVSState snvs; IMX7SNVSState snvs;
IMXI2CState i2c[FSL_IMX8MP_NUM_I2CS];
IMXSerialState uart[FSL_IMX8MP_NUM_UARTS]; IMXSerialState uart[FSL_IMX8MP_NUM_UARTS];
SDHCIState usdhc[FSL_IMX8MP_NUM_USDHCS]; SDHCIState usdhc[FSL_IMX8MP_NUM_USDHCS];
DesignwarePCIEHost pcie; DesignwarePCIEHost pcie;
@ -205,6 +208,11 @@ enum FslImx8mpIrqs {
FSL_IMX8MP_UART5_IRQ = 30, FSL_IMX8MP_UART5_IRQ = 30,
FSL_IMX8MP_UART6_IRQ = 16, FSL_IMX8MP_UART6_IRQ = 16,
FSL_IMX8MP_I2C1_IRQ = 35,
FSL_IMX8MP_I2C2_IRQ = 36,
FSL_IMX8MP_I2C3_IRQ = 37,
FSL_IMX8MP_I2C4_IRQ = 38,
FSL_IMX8MP_GPIO1_LOW_IRQ = 64, FSL_IMX8MP_GPIO1_LOW_IRQ = 64,
FSL_IMX8MP_GPIO1_HIGH_IRQ = 65, FSL_IMX8MP_GPIO1_HIGH_IRQ = 65,
FSL_IMX8MP_GPIO2_LOW_IRQ = 66, FSL_IMX8MP_GPIO2_LOW_IRQ = 66,
@ -216,6 +224,9 @@ enum FslImx8mpIrqs {
FSL_IMX8MP_GPIO5_LOW_IRQ = 72, FSL_IMX8MP_GPIO5_LOW_IRQ = 72,
FSL_IMX8MP_GPIO5_HIGH_IRQ = 73, FSL_IMX8MP_GPIO5_HIGH_IRQ = 73,
FSL_IMX8MP_I2C5_IRQ = 76,
FSL_IMX8MP_I2C6_IRQ = 77,
FSL_IMX8MP_PCI_INTA_IRQ = 126, FSL_IMX8MP_PCI_INTA_IRQ = 126,
FSL_IMX8MP_PCI_INTB_IRQ = 125, FSL_IMX8MP_PCI_INTB_IRQ = 125,
FSL_IMX8MP_PCI_INTC_IRQ = 124, FSL_IMX8MP_PCI_INTC_IRQ = 124,