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tcg: Merge opcode arguments into TCGOp
Rather than have a separate buffer of 10*max_ops entries, give each opcode 10 entries. The result is actually a bit smaller and should have slightly more cache locality. Reviewed-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson
Richard Henderson
parent
3d7196d43b
commit
75e8b9b7aa
4 changed files with 98 additions and 142 deletions
98
tcg/tcg.c
98
tcg/tcg.c
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@ -471,7 +471,6 @@ void tcg_func_start(TCGContext *s)
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s->gen_op_buf[0].next = 1;
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s->gen_op_buf[0].prev = 0;
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s->gen_next_op_idx = 1;
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s->gen_next_parm_idx = 0;
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}
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static inline int temp_idx(TCGContext *s, TCGTemp *ts)
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@ -980,9 +979,10 @@ bool tcg_op_supported(TCGOpcode op)
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void tcg_gen_callN(TCGContext *s, void *func, TCGArg ret,
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int nargs, TCGArg *args)
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{
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int i, real_args, nb_rets, pi, pi_first;
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int i, real_args, nb_rets, pi;
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unsigned sizemask, flags;
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TCGHelperInfo *info;
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TCGOp *op;
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info = g_hash_table_lookup(helper_table, (gpointer)func);
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flags = info->flags;
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@ -995,11 +995,11 @@ void tcg_gen_callN(TCGContext *s, void *func, TCGArg ret,
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int orig_sizemask = sizemask;
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int orig_nargs = nargs;
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TCGv_i64 retl, reth;
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TCGArg split_args[MAX_OPC_PARAM];
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TCGV_UNUSED_I64(retl);
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TCGV_UNUSED_I64(reth);
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if (sizemask != 0) {
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TCGArg *split_args = __builtin_alloca(sizeof(TCGArg) * nargs * 2);
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for (i = real_args = 0; i < nargs; ++i) {
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int is_64bit = sizemask & (1 << (i+1)*2);
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if (is_64bit) {
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@ -1034,7 +1034,19 @@ void tcg_gen_callN(TCGContext *s, void *func, TCGArg ret,
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}
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#endif /* TCG_TARGET_EXTEND_ARGS */
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pi_first = pi = s->gen_next_parm_idx;
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i = s->gen_next_op_idx;
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tcg_debug_assert(i < OPC_BUF_SIZE);
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s->gen_op_buf[0].prev = i;
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s->gen_next_op_idx = i + 1;
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op = &s->gen_op_buf[i];
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/* Set links for sequential allocation during translation. */
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memset(op, 0, offsetof(TCGOp, args));
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op->opc = INDEX_op_call;
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op->prev = i - 1;
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op->next = i + 1;
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pi = 0;
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if (ret != TCG_CALL_DUMMY_ARG) {
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#if defined(__sparc__) && !defined(__arch64__) \
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&& !defined(CONFIG_TCG_INTERPRETER)
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@ -1044,31 +1056,33 @@ void tcg_gen_callN(TCGContext *s, void *func, TCGArg ret,
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two return temporaries, and reassemble below. */
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retl = tcg_temp_new_i64();
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reth = tcg_temp_new_i64();
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s->gen_opparam_buf[pi++] = GET_TCGV_I64(reth);
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s->gen_opparam_buf[pi++] = GET_TCGV_I64(retl);
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op->args[pi++] = GET_TCGV_I64(reth);
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op->args[pi++] = GET_TCGV_I64(retl);
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nb_rets = 2;
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} else {
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s->gen_opparam_buf[pi++] = ret;
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op->args[pi++] = ret;
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nb_rets = 1;
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}
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#else
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if (TCG_TARGET_REG_BITS < 64 && (sizemask & 1)) {
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#ifdef HOST_WORDS_BIGENDIAN
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s->gen_opparam_buf[pi++] = ret + 1;
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s->gen_opparam_buf[pi++] = ret;
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op->args[pi++] = ret + 1;
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op->args[pi++] = ret;
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#else
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s->gen_opparam_buf[pi++] = ret;
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s->gen_opparam_buf[pi++] = ret + 1;
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op->args[pi++] = ret;
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op->args[pi++] = ret + 1;
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#endif
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nb_rets = 2;
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} else {
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s->gen_opparam_buf[pi++] = ret;
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op->args[pi++] = ret;
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nb_rets = 1;
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}
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#endif
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} else {
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nb_rets = 0;
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}
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op->callo = nb_rets;
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real_args = 0;
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for (i = 0; i < nargs; i++) {
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int is_64bit = sizemask & (1 << (i+1)*2);
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@ -1076,7 +1090,7 @@ void tcg_gen_callN(TCGContext *s, void *func, TCGArg ret,
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#ifdef TCG_TARGET_CALL_ALIGN_ARGS
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/* some targets want aligned 64 bit args */
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if (real_args & 1) {
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s->gen_opparam_buf[pi++] = TCG_CALL_DUMMY_ARG;
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op->args[pi++] = TCG_CALL_DUMMY_ARG;
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real_args++;
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}
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#endif
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@ -1091,42 +1105,26 @@ void tcg_gen_callN(TCGContext *s, void *func, TCGArg ret,
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have to get more complicated to differentiate between
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stack arguments and register arguments. */
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#if defined(HOST_WORDS_BIGENDIAN) != defined(TCG_TARGET_STACK_GROWSUP)
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s->gen_opparam_buf[pi++] = args[i] + 1;
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s->gen_opparam_buf[pi++] = args[i];
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op->args[pi++] = args[i] + 1;
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op->args[pi++] = args[i];
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#else
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s->gen_opparam_buf[pi++] = args[i];
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s->gen_opparam_buf[pi++] = args[i] + 1;
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op->args[pi++] = args[i];
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op->args[pi++] = args[i] + 1;
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#endif
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real_args += 2;
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continue;
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}
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s->gen_opparam_buf[pi++] = args[i];
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op->args[pi++] = args[i];
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real_args++;
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}
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s->gen_opparam_buf[pi++] = (uintptr_t)func;
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s->gen_opparam_buf[pi++] = flags;
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op->args[pi++] = (uintptr_t)func;
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op->args[pi++] = flags;
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op->calli = real_args;
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i = s->gen_next_op_idx;
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tcg_debug_assert(i < OPC_BUF_SIZE);
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tcg_debug_assert(pi <= OPPARAM_BUF_SIZE);
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/* Set links for sequential allocation during translation. */
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s->gen_op_buf[i] = (TCGOp){
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.opc = INDEX_op_call,
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.callo = nb_rets,
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.calli = real_args,
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.args = pi_first,
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.prev = i - 1,
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.next = i + 1
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};
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/* Make sure the calli field didn't overflow. */
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tcg_debug_assert(s->gen_op_buf[i].calli == real_args);
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s->gen_op_buf[0].prev = i;
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s->gen_next_op_idx = i + 1;
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s->gen_next_parm_idx = pi;
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/* Make sure the fields didn't overflow. */
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tcg_debug_assert(op->calli == real_args);
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tcg_debug_assert(pi <= ARRAY_SIZE(op->args));
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#if defined(__sparc__) && !defined(__arch64__) \
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&& !defined(CONFIG_TCG_INTERPRETER)
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@ -1286,7 +1284,7 @@ void tcg_dump_ops(TCGContext *s)
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op = &s->gen_op_buf[oi];
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c = op->opc;
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def = &tcg_op_defs[c];
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args = &s->gen_opparam_buf[op->args];
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args = op->args;
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if (c == INDEX_op_insn_start) {
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col += qemu_log("%s ----", oi != s->gen_op_buf[0].next ? "\n" : "");
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@ -1570,20 +1568,16 @@ TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *old_op,
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TCGOpcode opc, int nargs)
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{
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int oi = s->gen_next_op_idx;
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int pi = s->gen_next_parm_idx;
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int prev = old_op->prev;
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int next = old_op - s->gen_op_buf;
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TCGOp *new_op;
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tcg_debug_assert(oi < OPC_BUF_SIZE);
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tcg_debug_assert(pi + nargs <= OPPARAM_BUF_SIZE);
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s->gen_next_op_idx = oi + 1;
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s->gen_next_parm_idx = pi + nargs;
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new_op = &s->gen_op_buf[oi];
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*new_op = (TCGOp){
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.opc = opc,
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.args = pi,
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.prev = prev,
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.next = next
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};
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@ -1597,20 +1591,16 @@ TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *old_op,
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TCGOpcode opc, int nargs)
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{
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int oi = s->gen_next_op_idx;
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int pi = s->gen_next_parm_idx;
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int prev = old_op - s->gen_op_buf;
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int next = old_op->next;
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TCGOp *new_op;
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tcg_debug_assert(oi < OPC_BUF_SIZE);
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tcg_debug_assert(pi + nargs <= OPPARAM_BUF_SIZE);
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s->gen_next_op_idx = oi + 1;
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s->gen_next_parm_idx = pi + nargs;
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new_op = &s->gen_op_buf[oi];
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*new_op = (TCGOp){
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.opc = opc,
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.args = pi,
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.prev = prev,
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.next = next
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};
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@ -1666,7 +1656,7 @@ static void liveness_pass_1(TCGContext *s, uint8_t *temp_state)
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TCGArg arg;
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TCGOp * const op = &s->gen_op_buf[oi];
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TCGArg * const args = &s->gen_opparam_buf[op->args];
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TCGArg * const args = op->args;
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TCGOpcode opc = op->opc;
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const TCGOpDef *def = &tcg_op_defs[opc];
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@ -1904,7 +1894,7 @@ static bool liveness_pass_2(TCGContext *s, uint8_t *temp_state)
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for (oi = s->gen_op_buf[0].next; oi != 0; oi = oi_next) {
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TCGOp *op = &s->gen_op_buf[oi];
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TCGArg *args = &s->gen_opparam_buf[op->args];
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TCGArg *args = op->args;
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TCGOpcode opc = op->opc;
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const TCGOpDef *def = &tcg_op_defs[opc];
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TCGLifeData arg_life = op->life;
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@ -1947,7 +1937,7 @@ static bool liveness_pass_2(TCGContext *s, uint8_t *temp_state)
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? INDEX_op_ld_i32
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: INDEX_op_ld_i64);
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TCGOp *lop = tcg_op_insert_before(s, op, lopc, 3);
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TCGArg *largs = &s->gen_opparam_buf[lop->args];
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TCGArg *largs = lop->args;
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largs[0] = dir;
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largs[1] = temp_idx(s, its->mem_base);
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@ -2019,7 +2009,7 @@ static bool liveness_pass_2(TCGContext *s, uint8_t *temp_state)
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? INDEX_op_st_i32
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: INDEX_op_st_i64);
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TCGOp *sop = tcg_op_insert_after(s, op, sopc, 3);
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TCGArg *sargs = &s->gen_opparam_buf[sop->args];
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TCGArg *sargs = sop->args;
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sargs[0] = dir;
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sargs[1] = temp_idx(s, its->mem_base);
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@ -2851,7 +2841,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
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num_insns = -1;
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for (oi = s->gen_op_buf[0].next; oi != 0; oi = oi_next) {
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TCGOp * const op = &s->gen_op_buf[oi];
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TCGArg * const args = &s->gen_opparam_buf[op->args];
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TCGArg * const args = op->args;
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TCGOpcode opc = op->opc;
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const TCGOpDef *def = &tcg_op_defs[opc];
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TCGLifeData arg_life = op->life;
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