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target/riscv: add vector stride load and store instructions
Vector strided operations access the first memory element at the base address, and then access subsequent elements at address increments given by the byte offset contained in the x register specified by rs2. Vector unit-stride operations access elements stored contiguously in memory starting from the base effective address. It can been seen as a special case of strided operations. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200701152549.1218-7-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
LIU Zhiwei
Alistair Francis
parent
f476f17740
commit
751538d5da
6 changed files with 914 additions and 0 deletions
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@ -15,6 +15,9 @@
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "tcg/tcg-op-gvec.h"
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#include "tcg/tcg-gvec-desc.h"
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#include "internals.h"
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static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
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{
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@ -77,3 +80,355 @@ static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli *a)
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tcg_temp_free(dst);
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return true;
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}
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/* vector register offset from env */
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static uint32_t vreg_ofs(DisasContext *s, int reg)
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{
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return offsetof(CPURISCVState, vreg) + reg * s->vlen / 8;
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}
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/* check functions */
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/*
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* In cpu_get_tb_cpu_state(), set VILL if RVV was not present.
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* So RVV is also be checked in this function.
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*/
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static bool vext_check_isa_ill(DisasContext *s)
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{
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return !s->vill;
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}
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/*
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* There are two rules check here.
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*
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* 1. Vector register numbers are multiples of LMUL. (Section 3.2)
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*
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* 2. For all widening instructions, the destination LMUL value must also be
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* a supported LMUL value. (Section 11.2)
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*/
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static bool vext_check_reg(DisasContext *s, uint32_t reg, bool widen)
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{
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/*
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* The destination vector register group results are arranged as if both
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* SEW and LMUL were at twice their current settings. (Section 11.2).
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*/
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int legal = widen ? 2 << s->lmul : 1 << s->lmul;
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return !((s->lmul == 0x3 && widen) || (reg % legal));
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}
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/*
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* There are two rules check here.
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*
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* 1. The destination vector register group for a masked vector instruction can
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* only overlap the source mask register (v0) when LMUL=1. (Section 5.3)
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*
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* 2. In widen instructions and some other insturctions, like vslideup.vx,
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* there is no need to check whether LMUL=1.
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*/
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static bool vext_check_overlap_mask(DisasContext *s, uint32_t vd, bool vm,
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bool force)
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{
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return (vm != 0 || vd != 0) || (!force && (s->lmul == 0));
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}
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/* The LMUL setting must be such that LMUL * NFIELDS <= 8. (Section 7.8) */
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static bool vext_check_nf(DisasContext *s, uint32_t nf)
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{
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return (1 << s->lmul) * nf <= 8;
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}
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/* common translation macro */
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#define GEN_VEXT_TRANS(NAME, SEQ, ARGTYPE, OP, CHECK) \
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static bool trans_##NAME(DisasContext *s, arg_##ARGTYPE *a)\
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{ \
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if (CHECK(s, a)) { \
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return OP(s, a, SEQ); \
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} \
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return false; \
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}
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/*
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*** unit stride load and store
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*/
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typedef void gen_helper_ldst_us(TCGv_ptr, TCGv_ptr, TCGv,
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TCGv_env, TCGv_i32);
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static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
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gen_helper_ldst_us *fn, DisasContext *s)
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{
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TCGv_ptr dest, mask;
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TCGv base;
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TCGv_i32 desc;
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TCGLabel *over = gen_new_label();
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tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
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dest = tcg_temp_new_ptr();
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mask = tcg_temp_new_ptr();
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base = tcg_temp_new();
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/*
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* As simd_desc supports at most 256 bytes, and in this implementation,
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* the max vector group length is 2048 bytes. So split it into two parts.
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*
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* The first part is vlen in bytes, encoded in maxsz of simd_desc.
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* The second part is lmul, encoded in data of simd_desc.
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*/
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desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
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gen_get_gpr(base, rs1);
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tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
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tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
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fn(dest, mask, base, cpu_env, desc);
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tcg_temp_free_ptr(dest);
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tcg_temp_free_ptr(mask);
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tcg_temp_free(base);
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tcg_temp_free_i32(desc);
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gen_set_label(over);
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return true;
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}
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static bool ld_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
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{
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uint32_t data = 0;
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gen_helper_ldst_us *fn;
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static gen_helper_ldst_us * const fns[2][7][4] = {
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/* masked unit stride load */
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{ { gen_helper_vlb_v_b_mask, gen_helper_vlb_v_h_mask,
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gen_helper_vlb_v_w_mask, gen_helper_vlb_v_d_mask },
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{ NULL, gen_helper_vlh_v_h_mask,
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gen_helper_vlh_v_w_mask, gen_helper_vlh_v_d_mask },
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{ NULL, NULL,
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gen_helper_vlw_v_w_mask, gen_helper_vlw_v_d_mask },
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{ gen_helper_vle_v_b_mask, gen_helper_vle_v_h_mask,
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gen_helper_vle_v_w_mask, gen_helper_vle_v_d_mask },
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{ gen_helper_vlbu_v_b_mask, gen_helper_vlbu_v_h_mask,
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gen_helper_vlbu_v_w_mask, gen_helper_vlbu_v_d_mask },
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{ NULL, gen_helper_vlhu_v_h_mask,
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gen_helper_vlhu_v_w_mask, gen_helper_vlhu_v_d_mask },
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{ NULL, NULL,
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gen_helper_vlwu_v_w_mask, gen_helper_vlwu_v_d_mask } },
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/* unmasked unit stride load */
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{ { gen_helper_vlb_v_b, gen_helper_vlb_v_h,
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gen_helper_vlb_v_w, gen_helper_vlb_v_d },
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{ NULL, gen_helper_vlh_v_h,
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gen_helper_vlh_v_w, gen_helper_vlh_v_d },
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{ NULL, NULL,
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gen_helper_vlw_v_w, gen_helper_vlw_v_d },
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{ gen_helper_vle_v_b, gen_helper_vle_v_h,
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gen_helper_vle_v_w, gen_helper_vle_v_d },
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{ gen_helper_vlbu_v_b, gen_helper_vlbu_v_h,
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gen_helper_vlbu_v_w, gen_helper_vlbu_v_d },
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{ NULL, gen_helper_vlhu_v_h,
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gen_helper_vlhu_v_w, gen_helper_vlhu_v_d },
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{ NULL, NULL,
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gen_helper_vlwu_v_w, gen_helper_vlwu_v_d } }
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};
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fn = fns[a->vm][seq][s->sew];
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if (fn == NULL) {
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return false;
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}
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data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
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data = FIELD_DP32(data, VDATA, VM, a->vm);
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data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
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data = FIELD_DP32(data, VDATA, NF, a->nf);
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return ldst_us_trans(a->rd, a->rs1, data, fn, s);
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}
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static bool ld_us_check(DisasContext *s, arg_r2nfvm* a)
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{
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return (vext_check_isa_ill(s) &&
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vext_check_overlap_mask(s, a->rd, a->vm, false) &&
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vext_check_reg(s, a->rd, false) &&
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vext_check_nf(s, a->nf));
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}
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GEN_VEXT_TRANS(vlb_v, 0, r2nfvm, ld_us_op, ld_us_check)
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GEN_VEXT_TRANS(vlh_v, 1, r2nfvm, ld_us_op, ld_us_check)
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GEN_VEXT_TRANS(vlw_v, 2, r2nfvm, ld_us_op, ld_us_check)
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GEN_VEXT_TRANS(vle_v, 3, r2nfvm, ld_us_op, ld_us_check)
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GEN_VEXT_TRANS(vlbu_v, 4, r2nfvm, ld_us_op, ld_us_check)
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GEN_VEXT_TRANS(vlhu_v, 5, r2nfvm, ld_us_op, ld_us_check)
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GEN_VEXT_TRANS(vlwu_v, 6, r2nfvm, ld_us_op, ld_us_check)
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static bool st_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
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{
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uint32_t data = 0;
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gen_helper_ldst_us *fn;
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static gen_helper_ldst_us * const fns[2][4][4] = {
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/* masked unit stride load and store */
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{ { gen_helper_vsb_v_b_mask, gen_helper_vsb_v_h_mask,
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gen_helper_vsb_v_w_mask, gen_helper_vsb_v_d_mask },
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{ NULL, gen_helper_vsh_v_h_mask,
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gen_helper_vsh_v_w_mask, gen_helper_vsh_v_d_mask },
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{ NULL, NULL,
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gen_helper_vsw_v_w_mask, gen_helper_vsw_v_d_mask },
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{ gen_helper_vse_v_b_mask, gen_helper_vse_v_h_mask,
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gen_helper_vse_v_w_mask, gen_helper_vse_v_d_mask } },
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/* unmasked unit stride store */
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{ { gen_helper_vsb_v_b, gen_helper_vsb_v_h,
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gen_helper_vsb_v_w, gen_helper_vsb_v_d },
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{ NULL, gen_helper_vsh_v_h,
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gen_helper_vsh_v_w, gen_helper_vsh_v_d },
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{ NULL, NULL,
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gen_helper_vsw_v_w, gen_helper_vsw_v_d },
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{ gen_helper_vse_v_b, gen_helper_vse_v_h,
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gen_helper_vse_v_w, gen_helper_vse_v_d } }
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};
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fn = fns[a->vm][seq][s->sew];
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if (fn == NULL) {
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return false;
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}
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data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
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data = FIELD_DP32(data, VDATA, VM, a->vm);
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data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
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data = FIELD_DP32(data, VDATA, NF, a->nf);
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return ldst_us_trans(a->rd, a->rs1, data, fn, s);
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}
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static bool st_us_check(DisasContext *s, arg_r2nfvm* a)
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{
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return (vext_check_isa_ill(s) &&
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vext_check_reg(s, a->rd, false) &&
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vext_check_nf(s, a->nf));
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}
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GEN_VEXT_TRANS(vsb_v, 0, r2nfvm, st_us_op, st_us_check)
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GEN_VEXT_TRANS(vsh_v, 1, r2nfvm, st_us_op, st_us_check)
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GEN_VEXT_TRANS(vsw_v, 2, r2nfvm, st_us_op, st_us_check)
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GEN_VEXT_TRANS(vse_v, 3, r2nfvm, st_us_op, st_us_check)
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/*
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*** stride load and store
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*/
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typedef void gen_helper_ldst_stride(TCGv_ptr, TCGv_ptr, TCGv,
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TCGv, TCGv_env, TCGv_i32);
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static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
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uint32_t data, gen_helper_ldst_stride *fn,
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DisasContext *s)
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{
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TCGv_ptr dest, mask;
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TCGv base, stride;
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TCGv_i32 desc;
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TCGLabel *over = gen_new_label();
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tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
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dest = tcg_temp_new_ptr();
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mask = tcg_temp_new_ptr();
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base = tcg_temp_new();
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stride = tcg_temp_new();
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desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
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gen_get_gpr(base, rs1);
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gen_get_gpr(stride, rs2);
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tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
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tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
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fn(dest, mask, base, stride, cpu_env, desc);
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tcg_temp_free_ptr(dest);
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tcg_temp_free_ptr(mask);
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tcg_temp_free(base);
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tcg_temp_free(stride);
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tcg_temp_free_i32(desc);
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gen_set_label(over);
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return true;
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}
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static bool ld_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
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{
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uint32_t data = 0;
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gen_helper_ldst_stride *fn;
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static gen_helper_ldst_stride * const fns[7][4] = {
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{ gen_helper_vlsb_v_b, gen_helper_vlsb_v_h,
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gen_helper_vlsb_v_w, gen_helper_vlsb_v_d },
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{ NULL, gen_helper_vlsh_v_h,
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gen_helper_vlsh_v_w, gen_helper_vlsh_v_d },
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{ NULL, NULL,
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gen_helper_vlsw_v_w, gen_helper_vlsw_v_d },
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{ gen_helper_vlse_v_b, gen_helper_vlse_v_h,
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gen_helper_vlse_v_w, gen_helper_vlse_v_d },
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{ gen_helper_vlsbu_v_b, gen_helper_vlsbu_v_h,
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gen_helper_vlsbu_v_w, gen_helper_vlsbu_v_d },
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{ NULL, gen_helper_vlshu_v_h,
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gen_helper_vlshu_v_w, gen_helper_vlshu_v_d },
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{ NULL, NULL,
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gen_helper_vlswu_v_w, gen_helper_vlswu_v_d },
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};
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fn = fns[seq][s->sew];
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if (fn == NULL) {
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return false;
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}
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data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
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data = FIELD_DP32(data, VDATA, VM, a->vm);
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data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
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data = FIELD_DP32(data, VDATA, NF, a->nf);
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return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s);
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}
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static bool ld_stride_check(DisasContext *s, arg_rnfvm* a)
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{
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return (vext_check_isa_ill(s) &&
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vext_check_overlap_mask(s, a->rd, a->vm, false) &&
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vext_check_reg(s, a->rd, false) &&
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vext_check_nf(s, a->nf));
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}
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GEN_VEXT_TRANS(vlsb_v, 0, rnfvm, ld_stride_op, ld_stride_check)
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GEN_VEXT_TRANS(vlsh_v, 1, rnfvm, ld_stride_op, ld_stride_check)
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GEN_VEXT_TRANS(vlsw_v, 2, rnfvm, ld_stride_op, ld_stride_check)
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GEN_VEXT_TRANS(vlse_v, 3, rnfvm, ld_stride_op, ld_stride_check)
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GEN_VEXT_TRANS(vlsbu_v, 4, rnfvm, ld_stride_op, ld_stride_check)
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GEN_VEXT_TRANS(vlshu_v, 5, rnfvm, ld_stride_op, ld_stride_check)
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GEN_VEXT_TRANS(vlswu_v, 6, rnfvm, ld_stride_op, ld_stride_check)
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static bool st_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
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{
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uint32_t data = 0;
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gen_helper_ldst_stride *fn;
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static gen_helper_ldst_stride * const fns[4][4] = {
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/* masked stride store */
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{ gen_helper_vssb_v_b, gen_helper_vssb_v_h,
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gen_helper_vssb_v_w, gen_helper_vssb_v_d },
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{ NULL, gen_helper_vssh_v_h,
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gen_helper_vssh_v_w, gen_helper_vssh_v_d },
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{ NULL, NULL,
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gen_helper_vssw_v_w, gen_helper_vssw_v_d },
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{ gen_helper_vsse_v_b, gen_helper_vsse_v_h,
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gen_helper_vsse_v_w, gen_helper_vsse_v_d }
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};
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data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
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data = FIELD_DP32(data, VDATA, VM, a->vm);
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data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
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data = FIELD_DP32(data, VDATA, NF, a->nf);
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fn = fns[seq][s->sew];
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if (fn == NULL) {
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return false;
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}
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return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s);
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}
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static bool st_stride_check(DisasContext *s, arg_rnfvm* a)
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{
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return (vext_check_isa_ill(s) &&
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vext_check_reg(s, a->rd, false) &&
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vext_check_nf(s, a->nf));
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}
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GEN_VEXT_TRANS(vssb_v, 0, rnfvm, st_stride_op, st_stride_check)
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GEN_VEXT_TRANS(vssh_v, 1, rnfvm, st_stride_op, st_stride_check)
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GEN_VEXT_TRANS(vssw_v, 2, rnfvm, st_stride_op, st_stride_check)
|
||||
GEN_VEXT_TRANS(vsse_v, 3, rnfvm, st_stride_op, st_stride_check)
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue