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MIPS patches 2016-07-12

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Changes:
 * support 10-bit ASIDs
 * MIPS64R6-generic renamed to I6400
 * initial GIC support
 * implement RESET_BASE register in CM GCR
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Merge remote-tracking branch 'remotes/lalrae/tags/mips-20160712' into staging

MIPS patches 2016-07-12

Changes:
* support 10-bit ASIDs
* MIPS64R6-generic renamed to I6400
* initial GIC support
* implement RESET_BASE register in CM GCR

# gpg: Signature made Tue 12 Jul 2016 11:49:50 BST
# gpg:                using RSA key 0x52118E3C0B29DA6B
# gpg: Good signature from "Leon Alrae <leon.alrae@imgtec.com>"
# Primary key fingerprint: 8DD3 2F98 5495 9D66 35D4  4FC0 5211 8E3C 0B29 DA6B

* remotes/lalrae/tags/mips-20160712:
  target-mips: enable 10-bit ASIDs in I6400 CPU
  target-mips: support CP0.Config4.AE bit
  target-mips: change ASID type to hold more than 8 bits
  target-mips: add ASID mask field and replace magic values
  target-mips: replace MIPS64R6-generic with the real I6400 CPU model
  hw/mips_cmgcr: implement RESET_BASE register in CM GCR
  hw/mips_cpc: make VP correctly start from the reset vector
  target-mips: add exception base to MIPS CPU
  hw/mips/cps: create GIC block inside CPS
  hw/mips: implement Global Interrupt Controller
  hw/mips: implement GIC Interval Timer

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2016-07-12 12:34:41 +01:00
commit 74e1b782b3
18 changed files with 1059 additions and 56 deletions
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46
include/hw/timer/mips_gictimer.h Normal file
View file

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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2016 Imagination Technologies
*
*/
#ifndef _MIPS_GICTIMER_H_
#define _MIPS_GICTIMER_H_
typedef struct MIPSGICTimerVPState MIPSGICTimerVPState;
typedef struct MIPSGICTimerState MIPSGICTimerState;
typedef void MIPSGICTimerCB(void *opaque, uint32_t vp_index);
struct MIPSGICTimerVPState {
QEMUTimer *qtimer;
uint32_t vp_index;
uint32_t comparelo;
MIPSGICTimerState *gictimer;
};
struct MIPSGICTimerState {
void *opaque;
uint8_t countstop;
uint32_t sh_counterlo;
int32_t num_vps;
MIPSGICTimerVPState *vptimers;
MIPSGICTimerCB *cb;
};
uint32_t mips_gictimer_get_sh_count(MIPSGICTimerState *gic);
void mips_gictimer_store_sh_count(MIPSGICTimerState *gic, uint64_t count);
uint32_t mips_gictimer_get_vp_compare(MIPSGICTimerState *gictimer,
uint32_t vp_index);
void mips_gictimer_store_vp_compare(MIPSGICTimerState *gic, uint32_t vp_index,
uint64_t compare);
uint8_t mips_gictimer_get_countstop(MIPSGICTimerState *gic);
void mips_gictimer_start_count(MIPSGICTimerState *gic);
void mips_gictimer_stop_count(MIPSGICTimerState *gic);
MIPSGICTimerState *mips_gictimer_init(void *opaque, uint32_t nvps,
MIPSGICTimerCB *cb);
#endif /* _MIPS_GICTIMER_H_ */