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MIPS patches 2016-07-12

Browse source 
Changes:
 * support 10-bit ASIDs
 * MIPS64R6-generic renamed to I6400
 * initial GIC support
 * implement RESET_BASE register in CM GCR
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Merge remote-tracking branch 'remotes/lalrae/tags/mips-20160712' into staging

MIPS patches 2016-07-12

Changes:
* support 10-bit ASIDs
* MIPS64R6-generic renamed to I6400
* initial GIC support
* implement RESET_BASE register in CM GCR

# gpg: Signature made Tue 12 Jul 2016 11:49:50 BST
# gpg:                using RSA key 0x52118E3C0B29DA6B
# gpg: Good signature from "Leon Alrae <leon.alrae@imgtec.com>"
# Primary key fingerprint: 8DD3 2F98 5495 9D66 35D4  4FC0 5211 8E3C 0B29 DA6B

* remotes/lalrae/tags/mips-20160712:
  target-mips: enable 10-bit ASIDs in I6400 CPU
  target-mips: support CP0.Config4.AE bit
  target-mips: change ASID type to hold more than 8 bits
  target-mips: add ASID mask field and replace magic values
  target-mips: replace MIPS64R6-generic with the real I6400 CPU model
  hw/mips_cmgcr: implement RESET_BASE register in CM GCR
  hw/mips_cpc: make VP correctly start from the reset vector
  target-mips: add exception base to MIPS CPU
  hw/mips/cps: create GIC block inside CPS
  hw/mips: implement Global Interrupt Controller
  hw/mips: implement GIC Interval Timer

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2016-07-12 12:34:41 +01:00
commit 74e1b782b3
18 changed files with 1059 additions and 56 deletions
Download patch file Download diff file Expand all files Collapse all files

1
hw/intc/Makefile.objs
View file

@ -37,3 +37,4 @@ obj-$(CONFIG_S390_FLIC) += s390_flic.o
obj-$(CONFIG_S390_FLIC_KVM) += s390_flic_kvm.o
obj-$(CONFIG_ASPEED_SOC) += aspeed_vic.o
obj-$(CONFIG_ARM_GIC) += arm_gicv3_cpuif.o
obj-$(CONFIG_MIPS_CPS) += mips_gic.o

460
hw/intc/mips_gic.c Normal file
View file

@ -0,0 +1,460 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
* Authors: Sanjay Lal <sanjayl@kymasys.com>
*
* Copyright (C) 2016 Imagination Technologies
*/
#include "qemu/osdep.h"
#include "qemu/log.h"
#include "qapi/error.h"
#include "hw/hw.h"
#include "hw/sysbus.h"
#include "exec/memory.h"
#include "sysemu/sysemu.h"
#include "sysemu/kvm.h"
#include "kvm_mips.h"
#include "hw/intc/mips_gic.h"
static void mips_gic_set_vp_irq(MIPSGICState *gic, int vp, int pin, int level)
{
int ored_level = level;
int i;
/* ORing pending registers sharing same pin */
if (!ored_level) {
for (i = 0; i < gic->num_irq; i++) {
if ((gic->irq_state[i].map_pin & GIC_MAP_MSK) == pin &&
gic->irq_state[i].map_vp == vp &&
gic->irq_state[i].enabled) {
ored_level |= gic->irq_state[i].pending;
}
if (ored_level) {
/* no need to iterate all interrupts */
break;
}
}
if (((gic->vps[vp].compare_map & GIC_MAP_MSK) == pin) &&
(gic->vps[vp].mask & GIC_VP_MASK_CMP_MSK)) {
/* ORing with local pending register (count/compare) */
ored_level |= (gic->vps[vp].pend & GIC_VP_MASK_CMP_MSK) >>
GIC_VP_MASK_CMP_SHF;
}
}
if (kvm_enabled()) {
kvm_mips_set_ipi_interrupt(mips_env_get_cpu(gic->vps[vp].env),
pin + GIC_CPU_PIN_OFFSET,
ored_level);
} else {
qemu_set_irq(gic->vps[vp].env->irq[pin + GIC_CPU_PIN_OFFSET],
ored_level);
}
}
static void gic_set_irq(void *opaque, int n_IRQ, int level)
{
MIPSGICState *gic = (MIPSGICState *) opaque;
int vp = gic->irq_state[n_IRQ].map_vp;
int pin = gic->irq_state[n_IRQ].map_pin & GIC_MAP_MSK;
gic->irq_state[n_IRQ].pending = (uint8_t) level;
if (!gic->irq_state[n_IRQ].enabled) {
/* GIC interrupt source disabled */
return;
}
if (vp < 0 || vp >= gic->num_vps) {
return;
}
mips_gic_set_vp_irq(gic, vp, pin, level);
}
#define OFFSET_CHECK(c) \
do { \
if (!(c)) { \
goto bad_offset; \
} \
} while (0)
/* GIC Read VP Local/Other Registers */
static uint64_t gic_read_vp(MIPSGICState *gic, uint32_t vp_index, hwaddr addr,
unsigned size)
{
switch (addr) {
case GIC_VP_CTL_OFS:
return gic->vps[vp_index].ctl;
case GIC_VP_PEND_OFS:
mips_gictimer_get_sh_count(gic->gic_timer);
return gic->vps[vp_index].pend;
case GIC_VP_MASK_OFS:
return gic->vps[vp_index].mask;
case GIC_VP_COMPARE_MAP_OFS:
return gic->vps[vp_index].compare_map;
case GIC_VP_OTHER_ADDR_OFS:
return gic->vps[vp_index].other_addr;
case GIC_VP_IDENT_OFS:
return vp_index;
case GIC_VP_COMPARE_LO_OFS:
return mips_gictimer_get_vp_compare(gic->gic_timer, vp_index);
case GIC_VP_COMPARE_HI_OFS:
return 0;
default:
qemu_log_mask(LOG_UNIMP, "Read %d bytes at GIC offset LOCAL/OTHER 0x%"
PRIx64 "\n", size, addr);
break;
}
return 0;
}
static uint64_t gic_read(void *opaque, hwaddr addr, unsigned size)
{
MIPSGICState *gic = (MIPSGICState *) opaque;
uint32_t vp_index = current_cpu->cpu_index;
uint64_t ret = 0;
int i, base, irq_src;
uint32_t other_index;
switch (addr) {
case GIC_SH_CONFIG_OFS:
ret = gic->sh_config | (mips_gictimer_get_countstop(gic->gic_timer) <<
GIC_SH_CONFIG_COUNTSTOP_SHF);
break;
case GIC_SH_COUNTERLO_OFS:
ret = mips_gictimer_get_sh_count(gic->gic_timer);
break;
case GIC_SH_COUNTERHI_OFS:
ret = 0;
break;
case GIC_SH_PEND_OFS ... GIC_SH_PEND_LAST_OFS:
/* each bit represents pending status for an interrupt pin */
base = (addr - GIC_SH_PEND_OFS) * 8;
OFFSET_CHECK((base + size * 8) <= gic->num_irq);
for (i = 0; i < size * 8; i++) {
ret |= (uint64_t) (gic->irq_state[base + i].pending) << i;
}
break;
case GIC_SH_MASK_OFS ... GIC_SH_MASK_LAST_OFS:
/* each bit represents status for an interrupt pin */
base = (addr - GIC_SH_MASK_OFS) * 8;
OFFSET_CHECK((base + size * 8) <= gic->num_irq);
for (i = 0; i < size * 8; i++) {
ret |= (uint64_t) (gic->irq_state[base + i].enabled) << i;
}
break;
case GIC_SH_MAP0_PIN_OFS ... GIC_SH_MAP255_PIN_OFS:
/* 32 bits per a pin */
irq_src = (addr - GIC_SH_MAP0_PIN_OFS) / 4;
OFFSET_CHECK(irq_src < gic->num_irq);
ret = gic->irq_state[irq_src].map_pin;
break;
case GIC_SH_MAP0_VP_OFS ... GIC_SH_MAP255_VP_LAST_OFS:
/* up to 32 bytes per a pin */
irq_src = (addr - GIC_SH_MAP0_VP_OFS) / 32;
OFFSET_CHECK(irq_src < gic->num_irq);
if ((gic->irq_state[irq_src].map_vp) >= 0) {
ret = (uint64_t) 1 << (gic->irq_state[irq_src].map_vp);
} else {
ret = 0;
}
break;
/* VP-Local Register */
case VP_LOCAL_SECTION_OFS ... (VP_LOCAL_SECTION_OFS + GIC_VL_BRK_GROUP):
ret = gic_read_vp(gic, vp_index, addr - VP_LOCAL_SECTION_OFS, size);
break;
/* VP-Other Register */
case VP_OTHER_SECTION_OFS ... (VP_OTHER_SECTION_OFS + GIC_VL_BRK_GROUP):
other_index = gic->vps[vp_index].other_addr;
ret = gic_read_vp(gic, other_index, addr - VP_OTHER_SECTION_OFS, size);
break;
/* User-Mode Visible section */
case USM_VISIBLE_SECTION_OFS + GIC_USER_MODE_COUNTERLO:
ret = mips_gictimer_get_sh_count(gic->gic_timer);
break;
case USM_VISIBLE_SECTION_OFS + GIC_USER_MODE_COUNTERHI:
ret = 0;
break;
default:
qemu_log_mask(LOG_UNIMP, "Read %d bytes at GIC offset 0x%" PRIx64 "\n",
size, addr);
break;
}
return ret;
bad_offset:
qemu_log_mask(LOG_GUEST_ERROR, "Wrong GIC offset at 0x%" PRIx64 "\n", addr);
return 0;
}
static void gic_timer_expire_cb(void *opaque, uint32_t vp_index)
{
MIPSGICState *gic = opaque;
gic->vps[vp_index].pend |= (1 << GIC_LOCAL_INT_COMPARE);
if (gic->vps[vp_index].pend &
(gic->vps[vp_index].mask & GIC_VP_MASK_CMP_MSK)) {
if (gic->vps[vp_index].compare_map & GIC_MAP_TO_PIN_MSK) {
/* it is safe to set the irq high regardless of other GIC IRQs */
uint32_t pin = (gic->vps[vp_index].compare_map & GIC_MAP_MSK);
qemu_irq_raise(gic->vps[vp_index].env->irq
[pin + GIC_CPU_PIN_OFFSET]);
}
}
}
static void gic_timer_store_vp_compare(MIPSGICState *gic, uint32_t vp_index,
uint64_t compare)
{
gic->vps[vp_index].pend &= ~(1 << GIC_LOCAL_INT_COMPARE);
if (gic->vps[vp_index].compare_map & GIC_MAP_TO_PIN_MSK) {
uint32_t pin = (gic->vps[vp_index].compare_map & GIC_MAP_MSK);
mips_gic_set_vp_irq(gic, vp_index, pin, 0);
}
mips_gictimer_store_vp_compare(gic->gic_timer, vp_index, compare);
}
/* GIC Write VP Local/Other Registers */
static void gic_write_vp(MIPSGICState *gic, uint32_t vp_index, hwaddr addr,
uint64_t data, unsigned size)
{
switch (addr) {
case GIC_VP_CTL_OFS:
/* EIC isn't supported */
break;
case GIC_VP_RMASK_OFS:
gic->vps[vp_index].mask &= ~(data & GIC_VP_SET_RESET_MSK) &
GIC_VP_SET_RESET_MSK;
break;
case GIC_VP_SMASK_OFS:
gic->vps[vp_index].mask |= data & GIC_VP_SET_RESET_MSK;
break;
case GIC_VP_COMPARE_MAP_OFS:
/* EIC isn't supported */
OFFSET_CHECK((data & GIC_MAP_MSK) <= GIC_CPU_INT_MAX);
gic->vps[vp_index].compare_map = data & GIC_MAP_TO_PIN_REG_MSK;
break;
case GIC_VP_OTHER_ADDR_OFS:
OFFSET_CHECK(data < gic->num_vps);
gic->vps[vp_index].other_addr = data;
break;
case GIC_VP_COMPARE_LO_OFS:
gic_timer_store_vp_compare(gic, vp_index, data);
break;
default:
qemu_log_mask(LOG_UNIMP, "Write %d bytes at GIC offset LOCAL/OTHER "
"0x%" PRIx64" 0x%08" PRIx64 "\n", size, addr, data);
break;
}
return;
bad_offset:
qemu_log_mask(LOG_GUEST_ERROR, "Wrong GIC offset at 0x%" PRIx64 "\n", addr);
return;
}
static void gic_write(void *opaque, hwaddr addr, uint64_t data, unsigned size)
{
int intr;
MIPSGICState *gic = (MIPSGICState *) opaque;
uint32_t vp_index = current_cpu->cpu_index;
int i, base, irq_src;
uint32_t other_index;
switch (addr) {
case GIC_SH_CONFIG_OFS:
{
uint32_t pre_cntstop = mips_gictimer_get_countstop(gic->gic_timer);
uint32_t new_cntstop = (data & GIC_SH_CONFIG_COUNTSTOP_MSK) >>
GIC_SH_CONFIG_COUNTSTOP_SHF;
if (pre_cntstop != new_cntstop) {
if (new_cntstop == 1) {
mips_gictimer_stop_count(gic->gic_timer);
} else {
mips_gictimer_start_count(gic->gic_timer);
}
}
}
break;
case GIC_SH_COUNTERLO_OFS:
if (mips_gictimer_get_countstop(gic->gic_timer)) {
mips_gictimer_store_sh_count(gic->gic_timer, data);
}
break;
case GIC_SH_RMASK_OFS ... GIC_SH_RMASK_LAST_OFS:
/* up to 64 bits per a pin */
base = (addr - GIC_SH_RMASK_OFS) * 8;
OFFSET_CHECK((base + size * 8) <= gic->num_irq);
for (i = 0; i < size * 8; i++) {
gic->irq_state[base + i].enabled &= !((data >> i) & 1);
}
break;
case GIC_SH_WEDGE_OFS:
/* Figure out which VP/HW Interrupt this maps to */
intr = data & ~GIC_SH_WEDGE_RW_MSK;
/* Mask/Enabled Checks */
OFFSET_CHECK(intr < gic->num_irq);
if (data & GIC_SH_WEDGE_RW_MSK) {
gic_set_irq(gic, intr, 1);
} else {
gic_set_irq(gic, intr, 0);
}
break;
case GIC_SH_SMASK_OFS ... GIC_SH_SMASK_LAST_OFS:
/* up to 64 bits per a pin */
base = (addr - GIC_SH_SMASK_OFS) * 8;
OFFSET_CHECK((base + size * 8) <= gic->num_irq);
for (i = 0; i < size * 8; i++) {
gic->irq_state[base + i].enabled |= (data >> i) & 1;
}
break;
case GIC_SH_MAP0_PIN_OFS ... GIC_SH_MAP255_PIN_OFS:
/* 32 bits per a pin */
irq_src = (addr - GIC_SH_MAP0_PIN_OFS) / 4;
OFFSET_CHECK(irq_src < gic->num_irq);
/* EIC isn't supported */
OFFSET_CHECK((data & GIC_MAP_MSK) <= GIC_CPU_INT_MAX);
gic->irq_state[irq_src].map_pin = data & GIC_MAP_TO_PIN_REG_MSK;
break;
case GIC_SH_MAP0_VP_OFS ... GIC_SH_MAP255_VP_LAST_OFS:
/* up to 32 bytes per a pin */
irq_src = (addr - GIC_SH_MAP0_VP_OFS) / 32;
OFFSET_CHECK(irq_src < gic->num_irq);
data = data ? ctz64(data) : -1;
OFFSET_CHECK(data < gic->num_vps);
gic->irq_state[irq_src].map_vp = data;
break;
case VP_LOCAL_SECTION_OFS ... (VP_LOCAL_SECTION_OFS + GIC_VL_BRK_GROUP):
gic_write_vp(gic, vp_index, addr - VP_LOCAL_SECTION_OFS, data, size);
break;
case VP_OTHER_SECTION_OFS ... (VP_OTHER_SECTION_OFS + GIC_VL_BRK_GROUP):
other_index = gic->vps[vp_index].other_addr;
gic_write_vp(gic, other_index, addr - VP_OTHER_SECTION_OFS, data, size);
break;
case USM_VISIBLE_SECTION_OFS + GIC_USER_MODE_COUNTERLO:
case USM_VISIBLE_SECTION_OFS + GIC_USER_MODE_COUNTERHI:
/* do nothing. Read-only section */
break;
default:
qemu_log_mask(LOG_UNIMP, "Write %d bytes at GIC offset 0x%" PRIx64
" 0x%08" PRIx64 "\n", size, addr, data);
break;
}
return;
bad_offset:
qemu_log_mask(LOG_GUEST_ERROR, "Wrong GIC offset at 0x%" PRIx64 "\n", addr);
}
static void gic_reset(void *opaque)
{
int i;
MIPSGICState *gic = (MIPSGICState *) opaque;
int numintrs = (gic->num_irq / 8) - 1;
gic->sh_config = /* COUNTSTOP = 0 it is accessible via MIPSGICTimer*/
/* CounterHi not implemented */
(0 << GIC_SH_CONFIG_COUNTBITS_SHF) |
(numintrs << GIC_SH_CONFIG_NUMINTRS_SHF) |
(gic->num_vps << GIC_SH_CONFIG_PVPS_SHF);
for (i = 0; i < gic->num_vps; i++) {
gic->vps[i].ctl = 0x0;
gic->vps[i].pend = 0x0;
/* PERFCNT, TIMER and WD not implemented */
gic->vps[i].mask = 0x32;
gic->vps[i].compare_map = GIC_MAP_TO_PIN_MSK;
mips_gictimer_store_vp_compare(gic->gic_timer, i, 0xffffffff);
gic->vps[i].other_addr = 0x0;
}
for (i = 0; i < gic->num_irq; i++) {
gic->irq_state[i].enabled = 0;
gic->irq_state[i].pending = 0;
gic->irq_state[i].map_pin = GIC_MAP_TO_PIN_MSK;
gic->irq_state[i].map_vp = -1;
}
mips_gictimer_store_sh_count(gic->gic_timer, 0);
/* COUNTSTOP = 0 */
mips_gictimer_start_count(gic->gic_timer);
}
static const MemoryRegionOps gic_ops = {
.read = gic_read,
.write = gic_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.impl = {
.max_access_size = 8,
},
};
static void mips_gic_init(Object *obj)
{
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
MIPSGICState *s = MIPS_GIC(obj);
memory_region_init_io(&s->mr, OBJECT(s), &gic_ops, s,
"mips-gic", GIC_ADDRSPACE_SZ);
sysbus_init_mmio(sbd, &s->mr);
qemu_register_reset(gic_reset, s);
}
static void mips_gic_realize(DeviceState *dev, Error **errp)
{
MIPSGICState *s = MIPS_GIC(dev);
CPUState *cs = first_cpu;
int i;
if (s->num_vps > GIC_MAX_VPS) {
error_setg(errp, "Exceeded maximum CPUs %d", s->num_vps);
return;
}
if ((s->num_irq > GIC_MAX_INTRS) || (s->num_irq % 8) || (s->num_irq <= 0)) {
error_setg(errp, "GIC supports up to %d external interrupts in "
"multiples of 8 : %d", GIC_MAX_INTRS, s->num_irq);
return;
}
s->vps = g_new(MIPSGICVPState, s->num_vps);
s->irq_state = g_new(MIPSGICIRQState, s->num_irq);
/* Register the env for all VPs with the GIC */
for (i = 0; i < s->num_vps; i++) {
if (cs != NULL) {
s->vps[i].env = cs->env_ptr;
cs = CPU_NEXT(cs);
} else {
error_setg(errp,
"Unable to initialize GIC, CPUState for CPU#%d not valid.", i);
return;
}
}
s->gic_timer = mips_gictimer_init(s, s->num_vps, gic_timer_expire_cb);
qdev_init_gpio_in(dev, gic_set_irq, s->num_irq);
for (i = 0; i < s->num_irq; i++) {
s->irq_state[i].irq = qdev_get_gpio_in(dev, i);
}
}
static Property mips_gic_properties[] = {
DEFINE_PROP_INT32("num-vp", MIPSGICState, num_vps, 1),
DEFINE_PROP_INT32("num-irq", MIPSGICState, num_irq, 256),
DEFINE_PROP_END_OF_LIST(),
};
static void mips_gic_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->props = mips_gic_properties;
dc->realize = mips_gic_realize;
}
static const TypeInfo mips_gic_info = {
.name = TYPE_MIPS_GIC,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(MIPSGICState),
.instance_init = mips_gic_init,
.class_init = mips_gic_class_init,
};
static void mips_gic_register_types(void)
{
type_register_static(&mips_gic_info);
}
type_init(mips_gic_register_types)

25
hw/mips/cps.c
View file

@ -26,13 +26,8 @@
qemu_irq get_cps_irq(MIPSCPSState *s, int pin_number)
{
MIPSCPU *cpu = MIPS_CPU(first_cpu);
CPUMIPSState *env = &cpu->env;
assert(pin_number < s->num_irq);
/* TODO: return GIC pins once implemented */
return env->irq[pin_number];
return s->gic.irq_state[pin_number].irq;
}
static void mips_cps_init(Object *obj)
@ -130,6 +125,21 @@ static void mips_cps_realize(DeviceState *dev, Error **errp)
memory_region_add_subregion(&s->container, 0,
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpc), 0));
/* Global Interrupt Controller */
object_initialize(&s->gic, sizeof(s->gic), TYPE_MIPS_GIC);
qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default());
object_property_set_int(OBJECT(&s->gic), s->num_vp, "num-vp", &err);
object_property_set_int(OBJECT(&s->gic), 128, "num-irq", &err);
object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
if (err != NULL) {
error_propagate(errp, err);
return;
}
memory_region_add_subregion(&s->container, 0,
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gic), 0));
/* Global Configuration Registers */
gcr_base = env->CP0_CMGCRBase << 4;
@ -139,6 +149,7 @@ static void mips_cps_realize(DeviceState *dev, Error **errp)
object_property_set_int(OBJECT(&s->gcr), s->num_vp, "num-vp", &err);
object_property_set_int(OBJECT(&s->gcr), 0x800, "gcr-rev", &err);
object_property_set_int(OBJECT(&s->gcr), gcr_base, "gcr-base", &err);
object_property_set_link(OBJECT(&s->gcr), OBJECT(&s->gic.mr), "gic", &err);
object_property_set_link(OBJECT(&s->gcr), OBJECT(&s->cpc.mr), "cpc", &err);
object_property_set_bool(OBJECT(&s->gcr), true, "realized", &err);
if (err != NULL) {
@ -152,7 +163,7 @@ static void mips_cps_realize(DeviceState *dev, Error **errp)
static Property mips_cps_properties[] = {
DEFINE_PROP_UINT32("num-vp", MIPSCPSState, num_vp, 1),
DEFINE_PROP_UINT32("num-irq", MIPSCPSState, num_irq, 8),
DEFINE_PROP_UINT32("num-irq", MIPSCPSState, num_irq, 256),
DEFINE_PROP_STRING("cpu-model", MIPSCPSState, cpu_model),
DEFINE_PROP_END_OF_LIST()
};

4
hw/mips/mips_malta.c
View file

@ -955,9 +955,7 @@ static void create_cps(MaltaState *s, const char *cpu_model,
sysbus_mmio_map_overlap(SYS_BUS_DEVICE(s->cps), 0, 0, 1);
/* FIXME: When GIC is present then we should use GIC's IRQ 3.
Until then CPS exposes CPU's IRQs thus use the default IRQ 2. */
*i8259_irq = get_cps_irq(s->cps, 2);
*i8259_irq = get_cps_irq(s->cps, 3);
*cbus_irq = NULL;
}

87
hw/misc/mips_cmgcr.c
View file

@ -17,12 +17,18 @@
#include "sysemu/sysemu.h"
#include "hw/misc/mips_cmgcr.h"
#include "hw/misc/mips_cpc.h"
#include "hw/intc/mips_gic.h"
static inline bool is_cpc_connected(MIPSGCRState *s)
{
return s->cpc_mr != NULL;
}
static inline bool is_gic_connected(MIPSGCRState *s)
{
return s->gic_mr != NULL;
}
static inline void update_cpc_base(MIPSGCRState *gcr, uint64_t val)
{
if (is_cpc_connected(gcr)) {
@ -36,10 +42,25 @@ static inline void update_cpc_base(MIPSGCRState *gcr, uint64_t val)
}
}
static inline void update_gic_base(MIPSGCRState *gcr, uint64_t val)
{
if (is_gic_connected(gcr)) {
gcr->gic_base = val & GCR_GIC_BASE_MSK;
memory_region_transaction_begin();
memory_region_set_address(gcr->gic_mr,
gcr->gic_base & GCR_GIC_BASE_GICBASE_MSK);
memory_region_set_enabled(gcr->gic_mr,
gcr->gic_base & GCR_GIC_BASE_GICEN_MSK);
memory_region_transaction_commit();
}
}
/* Read GCR registers */
static uint64_t gcr_read(void *opaque, hwaddr addr, unsigned size)
{
MIPSGCRState *gcr = (MIPSGCRState *) opaque;
MIPSGCRVPState *current_vps = &gcr->vps[current_cpu->cpu_index];
MIPSGCRVPState *other_vps = &gcr->vps[current_vps->other];
switch (addr) {
/* Global Control Block Register */
@ -50,8 +71,12 @@ static uint64_t gcr_read(void *opaque, hwaddr addr, unsigned size)
return gcr->gcr_base;
case GCR_REV_OFS:
return gcr->gcr_rev;
case GCR_GIC_BASE_OFS:
return gcr->gic_base;
case GCR_CPC_BASE_OFS:
return gcr->cpc_base;
case GCR_GIC_STATUS_OFS:
return is_gic_connected(gcr);
case GCR_CPC_STATUS_OFS:
return is_cpc_connected(gcr);
case GCR_L2_CONFIG_OFS:
@ -62,8 +87,14 @@ static uint64_t gcr_read(void *opaque, hwaddr addr, unsigned size)
case MIPS_COCB_OFS + GCR_CL_CONFIG_OFS:
/* Set PVP to # of VPs - 1 */
return gcr->num_vps - 1;
case MIPS_CLCB_OFS + GCR_CL_RESETBASE_OFS:
return current_vps->reset_base;
case MIPS_COCB_OFS + GCR_CL_RESETBASE_OFS:
return other_vps->reset_base;
case MIPS_CLCB_OFS + GCR_CL_OTHER_OFS:
return 0;
return current_vps->other;
case MIPS_COCB_OFS + GCR_CL_OTHER_OFS:
return other_vps->other;
default:
qemu_log_mask(LOG_UNIMP, "Read %d bytes at GCR offset 0x%" HWADDR_PRIx
"\n", size, addr);
@ -72,15 +103,46 @@ static uint64_t gcr_read(void *opaque, hwaddr addr, unsigned size)
return 0;
}
static inline target_ulong get_exception_base(MIPSGCRVPState *vps)
{
/* TODO: BEV_BASE and SELECT_BEV */
return (int32_t)(vps->reset_base & GCR_CL_RESET_BASE_RESETBASE_MSK);
}
/* Write GCR registers */
static void gcr_write(void *opaque, hwaddr addr, uint64_t data, unsigned size)
{
MIPSGCRState *gcr = (MIPSGCRState *)opaque;
MIPSGCRVPState *current_vps = &gcr->vps[current_cpu->cpu_index];
MIPSGCRVPState *other_vps = &gcr->vps[current_vps->other];
switch (addr) {
case GCR_GIC_BASE_OFS:
update_gic_base(gcr, data);
break;
case GCR_CPC_BASE_OFS:
update_cpc_base(gcr, data);
break;
case MIPS_CLCB_OFS + GCR_CL_RESETBASE_OFS:
current_vps->reset_base = data & GCR_CL_RESET_BASE_MSK;
cpu_set_exception_base(current_cpu->cpu_index,
get_exception_base(current_vps));
break;
case MIPS_COCB_OFS + GCR_CL_RESETBASE_OFS:
other_vps->reset_base = data & GCR_CL_RESET_BASE_MSK;
cpu_set_exception_base(current_vps->other,
get_exception_base(other_vps));
break;
case MIPS_CLCB_OFS + GCR_CL_OTHER_OFS:
if ((data & GCR_CL_OTHER_MSK) < gcr->num_vps) {
current_vps->other = data & GCR_CL_OTHER_MSK;
}
break;
case MIPS_COCB_OFS + GCR_CL_OTHER_OFS:
if ((data & GCR_CL_OTHER_MSK) < gcr->num_vps) {
other_vps->other = data & GCR_CL_OTHER_MSK;
}
break;
default:
qemu_log_mask(LOG_UNIMP, "Write %d bytes at GCR offset 0x%" HWADDR_PRIx
" 0x%" PRIx64 "\n", size, addr, data);
@ -102,6 +164,12 @@ static void mips_gcr_init(Object *obj)
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
MIPSGCRState *s = MIPS_GCR(obj);
object_property_add_link(obj, "gic", TYPE_MEMORY_REGION,
(Object **)&s->gic_mr,
qdev_prop_allow_set_link_before_realize,
OBJ_PROP_LINK_UNREF_ON_RELEASE,
&error_abort);
object_property_add_link(obj, "cpc", TYPE_MEMORY_REGION,
(Object **)&s->cpc_mr,
qdev_prop_allow_set_link_before_realize,
@ -116,8 +184,16 @@ static void mips_gcr_init(Object *obj)
static void mips_gcr_reset(DeviceState *dev)
{
MIPSGCRState *s = MIPS_GCR(dev);
int i;
update_gic_base(s, 0);
update_cpc_base(s, 0);
for (i = 0; i < s->num_vps; i++) {
s->vps[i].other = 0;
s->vps[i].reset_base = 0xBFC00000 & GCR_CL_RESET_BASE_MSK;
cpu_set_exception_base(i, get_exception_base(&s->vps[i]));
}
}
static const VMStateDescription vmstate_mips_gcr = {
@ -137,12 +213,21 @@ static Property mips_gcr_properties[] = {
DEFINE_PROP_END_OF_LIST(),
};
static void mips_gcr_realize(DeviceState *dev, Error **errp)
{
MIPSGCRState *s = MIPS_GCR(dev);
/* Create local set of registers for each VP */
s->vps = g_new(MIPSGCRVPState, s->num_vps);
}
static void mips_gcr_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->props = mips_gcr_properties;
dc->vmsd = &vmstate_mips_gcr;
dc->reset = mips_gcr_reset;
dc->realize = mips_gcr_realize;
}
static const TypeInfo mips_gcr_info = {

5
hw/misc/mips_cpc.c
View file

@ -37,7 +37,7 @@ static void cpc_run_vp(MIPSCPCState *cpc, uint64_t vp_run)
CPU_FOREACH(cs) {
uint64_t i = 1ULL << cs->cpu_index;
if (i & vp_run & ~cpc->vp_running) {
cpu_interrupt(cs, CPU_INTERRUPT_WAKE);
cpu_reset(cs);
cpc->vp_running |= i;
}
}
@ -50,8 +50,7 @@ static void cpc_stop_vp(MIPSCPCState *cpc, uint64_t vp_stop)
CPU_FOREACH(cs) {
uint64_t i = 1ULL << cs->cpu_index;
if (i & vp_stop & cpc->vp_running) {
cs->halted = 1;
cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
cpu_interrupt(cs, CPU_INTERRUPT_HALT);
cpc->vp_running &= ~i;
}
}

1
hw/timer/Makefile.objs
View file

@ -26,6 +26,7 @@ obj-$(CONFIG_OMAP) += omap_synctimer.o
obj-$(CONFIG_PXA2XX) += pxa2xx_timer.o
obj-$(CONFIG_SH4) += sh_timer.o
obj-$(CONFIG_DIGIC) += digic-timer.o
obj-$(CONFIG_MIPS_CPS) += mips_gictimer.o
obj-$(CONFIG_MC146818RTC) += mc146818rtc.o

142
hw/timer/mips_gictimer.c Normal file
View file

@ -0,0 +1,142 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2016 Imagination Technologies
*/
#include "qemu/osdep.h"
#include "hw/hw.h"
#include "hw/sysbus.h"
#include "qemu/timer.h"
#include "hw/timer/mips_gictimer.h"
#define TIMER_PERIOD 10 /* 10 ns period for 100 Mhz frequency */
static void gic_vptimer_update(MIPSGICTimerState *gictimer,
uint32_t vp_index, uint64_t now)
{
uint64_t next;
uint32_t wait;
wait = gictimer->vptimers[vp_index].comparelo - gictimer->sh_counterlo -
(uint32_t)(now / TIMER_PERIOD);
next = now + (uint64_t)wait * TIMER_PERIOD;
timer_mod(gictimer->vptimers[vp_index].qtimer, next);
}
static void gic_vptimer_expire(MIPSGICTimerState *gictimer, uint32_t vp_index,
uint64_t now)
{
if (gictimer->countstop) {
/* timer stopped */
return;
}
gictimer->cb(gictimer->opaque, vp_index);
gic_vptimer_update(gictimer, vp_index, now);
}
static void gic_vptimer_cb(void *opaque)
{
MIPSGICTimerVPState *vptimer = opaque;
MIPSGICTimerState *gictimer = vptimer->gictimer;
gic_vptimer_expire(gictimer, vptimer->vp_index,
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
}
uint32_t mips_gictimer_get_sh_count(MIPSGICTimerState *gictimer)
{
int i;
if (gictimer->countstop) {
return gictimer->sh_counterlo;
} else {
uint64_t now;
now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
for (i = 0; i < gictimer->num_vps; i++) {
if (timer_pending(gictimer->vptimers[i].qtimer)
&& timer_expired(gictimer->vptimers[i].qtimer, now)) {
/* The timer has already expired. */
gic_vptimer_expire(gictimer, i, now);
}
}
return gictimer->sh_counterlo + (uint32_t)(now / TIMER_PERIOD);
}
}
void mips_gictimer_store_sh_count(MIPSGICTimerState *gictimer, uint64_t count)
{
int i;
uint64_t now;
if (gictimer->countstop || !gictimer->vptimers[0].qtimer) {
gictimer->sh_counterlo = count;
} else {
/* Store new count register */
now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
gictimer->sh_counterlo = count - (uint32_t)(now / TIMER_PERIOD);
/* Update timer timer */
for (i = 0; i < gictimer->num_vps; i++) {
gic_vptimer_update(gictimer, i, now);
}
}
}
uint32_t mips_gictimer_get_vp_compare(MIPSGICTimerState *gictimer,
uint32_t vp_index)
{
return gictimer->vptimers[vp_index].comparelo;
}
void mips_gictimer_store_vp_compare(MIPSGICTimerState *gictimer,
uint32_t vp_index, uint64_t compare)
{
gictimer->vptimers[vp_index].comparelo = (uint32_t) compare;
gic_vptimer_update(gictimer, vp_index,
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
}
uint8_t mips_gictimer_get_countstop(MIPSGICTimerState *gictimer)
{
return gictimer->countstop;
}
void mips_gictimer_start_count(MIPSGICTimerState *gictimer)
{
gictimer->countstop = 0;
mips_gictimer_store_sh_count(gictimer, gictimer->sh_counterlo);
}
void mips_gictimer_stop_count(MIPSGICTimerState *gictimer)
{
int i;
gictimer->countstop = 1;
/* Store the current value */
gictimer->sh_counterlo +=
(uint32_t)(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / TIMER_PERIOD);
for (i = 0; i < gictimer->num_vps; i++) {
timer_del(gictimer->vptimers[i].qtimer);
}
}
MIPSGICTimerState *mips_gictimer_init(void *opaque, uint32_t nvps,
MIPSGICTimerCB *cb)
{
int i;
MIPSGICTimerState *gictimer = g_new(MIPSGICTimerState, 1);
gictimer->vptimers = g_new(MIPSGICTimerVPState, nvps);
gictimer->countstop = 1;
gictimer->num_vps = nvps;
gictimer->opaque = opaque;
gictimer->cb = cb;
for (i = 0; i < nvps; i++) {
gictimer->vptimers[i].gictimer = gictimer;
gictimer->vptimers[i].vp_index = i;
gictimer->vptimers[i].qtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
&gic_vptimer_cb,
&gictimer->vptimers[i]);
}
return gictimer;
}