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tcg: Merge INDEX_op_shr_{i32,i64}
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
edd6ba8a6b
commit
74dbd36f1f
7 changed files with 18 additions and 29 deletions
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@ -384,10 +384,10 @@ Shifts/Rotates
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- | *t0* = *t1* << *t2*
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| Unspecified behavior for negative or out-of-range shifts.
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* - shr_i32/i64 *t0*, *t1*, *t2*
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* - shr *t0*, *t1*, *t2*
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- | *t0* = *t1* >> *t2* (unsigned)
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| Unspecified behavior if *t2* < 0 or *t2* >= 32 (resp 64)
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| Unspecified behavior for negative or out-of-range shifts.
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* - sar_i32/i64 *t0*, *t1*, *t2*
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@ -59,6 +59,7 @@ DEF(orc, 1, 2, 0, TCG_OPF_INT)
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DEF(rems, 1, 2, 0, TCG_OPF_INT)
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DEF(remu, 1, 2, 0, TCG_OPF_INT)
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DEF(shl, 1, 2, 0, TCG_OPF_INT)
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DEF(shr, 1, 2, 0, TCG_OPF_INT)
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DEF(sub, 1, 2, 0, TCG_OPF_INT)
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DEF(xor, 1, 2, 0, TCG_OPF_INT)
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@ -75,7 +76,6 @@ DEF(st8_i32, 0, 2, 1, 0)
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DEF(st16_i32, 0, 2, 1, 0)
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DEF(st_i32, 0, 2, 1, 0)
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/* shifts/rotates */
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DEF(shr_i32, 1, 2, 0, 0)
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DEF(sar_i32, 1, 2, 0, 0)
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DEF(rotl_i32, 1, 2, 0, 0)
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DEF(rotr_i32, 1, 2, 0, 0)
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@ -115,7 +115,6 @@ DEF(st16_i64, 0, 2, 1, 0)
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DEF(st32_i64, 0, 2, 1, 0)
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DEF(st_i64, 0, 2, 1, 0)
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/* shifts/rotates */
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DEF(shr_i64, 1, 2, 0, 0)
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DEF(sar_i64, 1, 2, 0, 0)
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DEF(rotl_i64, 1, 2, 0, 0)
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DEF(rotr_i64, 1, 2, 0, 0)
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@ -452,10 +452,10 @@ static uint64_t do_constant_folding_2(TCGOpcode op, TCGType type,
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}
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return (uint64_t)x << (y & 63);
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case INDEX_op_shr_i32:
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return (uint32_t)x >> (y & 31);
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case INDEX_op_shr_i64:
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case INDEX_op_shr:
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if (type == TCG_TYPE_I32) {
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return (uint32_t)x >> (y & 31);
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}
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return (uint64_t)x >> (y & 63);
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case INDEX_op_sar_i32:
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@ -2342,7 +2342,6 @@ static int fold_setcond_zmask(OptContext *ctx, TCGOp *op, bool neg)
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static void fold_setcond_tst_pow2(OptContext *ctx, TCGOp *op, bool neg)
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{
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TCGOpcode shr_opc;
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TCGOpcode uext_opc = 0, sext_opc = 0;
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TCGCond cond = op->args[3];
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TCGArg ret, src1, src2;
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@ -2364,7 +2363,6 @@ static void fold_setcond_tst_pow2(OptContext *ctx, TCGOp *op, bool neg)
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switch (ctx->type) {
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case TCG_TYPE_I32:
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shr_opc = INDEX_op_shr_i32;
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if (TCG_TARGET_extract_valid(TCG_TYPE_I32, sh, 1)) {
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uext_opc = INDEX_op_extract_i32;
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}
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@ -2373,7 +2371,6 @@ static void fold_setcond_tst_pow2(OptContext *ctx, TCGOp *op, bool neg)
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}
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break;
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case TCG_TYPE_I64:
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shr_opc = INDEX_op_shr_i64;
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if (TCG_TARGET_extract_valid(TCG_TYPE_I64, sh, 1)) {
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uext_opc = INDEX_op_extract_i64;
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}
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@ -2402,7 +2399,7 @@ static void fold_setcond_tst_pow2(OptContext *ctx, TCGOp *op, bool neg)
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op->args[3] = 1;
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} else {
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if (sh) {
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op2 = opt_insert_before(ctx, op, shr_opc, 3);
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op2 = opt_insert_before(ctx, op, INDEX_op_shr, 3);
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op2->args[0] = ret;
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op2->args[1] = src1;
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op2->args[2] = arg_new_constant(ctx, sh);
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@ -2609,7 +2606,7 @@ static bool fold_shift(OptContext *ctx, TCGOp *op)
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* input sign repetitions.
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*/
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return fold_masks_s(ctx, op, s_mask);
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CASE_OP_32_64(shr):
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case INDEX_op_shr:
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/*
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* If the sign bit is known zero, then logical right shift
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* will not reduce the number of input sign repetitions.
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@ -3032,7 +3029,7 @@ void tcg_optimize(TCGContext *s)
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CASE_OP_32_64(rotr):
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CASE_OP_32_64(sar):
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case INDEX_op_shl:
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CASE_OP_32_64(shr):
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case INDEX_op_shr:
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done = fold_shift(&ctx, op);
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break;
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CASE_OP_32_64(setcond):
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@ -496,7 +496,7 @@ void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
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void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
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{
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tcg_gen_op3_i32(INDEX_op_shr_i32, ret, arg1, arg2);
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tcg_gen_op3_i32(INDEX_op_shr, ret, arg1, arg2);
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}
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void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
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@ -1615,7 +1615,7 @@ void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
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void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
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{
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if (TCG_TARGET_REG_BITS == 64) {
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tcg_gen_op3_i64(INDEX_op_shr_i64, ret, arg1, arg2);
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tcg_gen_op3_i64(INDEX_op_shr, ret, arg1, arg2);
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} else {
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gen_helper_shr_i64(ret, arg1, arg2);
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}
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@ -1043,8 +1043,7 @@ static const TCGOutOp * const all_outop[NB_OPS] = {
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OUTOP(INDEX_op_rems, TCGOutOpBinary, outop_rems),
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OUTOP(INDEX_op_remu, TCGOutOpBinary, outop_remu),
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OUTOP(INDEX_op_shl, TCGOutOpBinary, outop_shl),
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OUTOP(INDEX_op_shr_i32, TCGOutOpBinary, outop_shr),
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OUTOP(INDEX_op_shr_i64, TCGOutOpBinary, outop_shr),
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OUTOP(INDEX_op_shr, TCGOutOpBinary, outop_shr),
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OUTOP(INDEX_op_sub, TCGOutOpSubtract, outop_sub),
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OUTOP(INDEX_op_xor, TCGOutOpBinary, outop_xor),
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};
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@ -5423,8 +5422,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
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case INDEX_op_rems:
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case INDEX_op_remu:
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case INDEX_op_shl:
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case INDEX_op_shr_i32:
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case INDEX_op_shr_i64:
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case INDEX_op_shr:
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case INDEX_op_xor:
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{
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const TCGOutOpBinary *out =
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11
tcg/tci.c
11
tcg/tci.c
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@ -621,9 +621,9 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
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tci_args_rrr(insn, &r0, &r1, &r2);
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regs[r0] = regs[r1] << (regs[r2] % TCG_TARGET_REG_BITS);
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break;
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case INDEX_op_shr_i32:
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case INDEX_op_shr:
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tci_args_rrr(insn, &r0, &r1, &r2);
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regs[r0] = (uint32_t)regs[r1] >> (regs[r2] & 31);
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regs[r0] = regs[r1] >> (regs[r2] % TCG_TARGET_REG_BITS);
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break;
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case INDEX_op_sar_i32:
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tci_args_rrr(insn, &r0, &r1, &r2);
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@ -787,10 +787,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
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/* Shift/rotate operations (64 bit). */
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case INDEX_op_shr_i64:
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tci_args_rrr(insn, &r0, &r1, &r2);
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regs[r0] = regs[r1] >> (regs[r2] & 63);
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break;
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case INDEX_op_sar_i64:
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tci_args_rrr(insn, &r0, &r1, &r2);
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regs[r0] = (int64_t)regs[r1] >> (regs[r2] & 63);
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@ -1078,10 +1074,9 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
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case INDEX_op_rems:
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case INDEX_op_remu:
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case INDEX_op_shl:
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case INDEX_op_shr:
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case INDEX_op_sub:
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case INDEX_op_xor:
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case INDEX_op_shr_i32:
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case INDEX_op_shr_i64:
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case INDEX_op_sar_i32:
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case INDEX_op_sar_i64:
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case INDEX_op_rotl_i32:
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@ -792,7 +792,7 @@ static void tgen_shr(TCGContext *s, TCGType type,
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tcg_out_ext32u(s, TCG_REG_TMP, a1);
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a1 = TCG_REG_TMP;
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}
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tcg_out_op_rrr(s, glue(INDEX_op_shr_i,TCG_TARGET_REG_BITS), a0, a1, a2);
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tcg_out_op_rrr(s, INDEX_op_shr, a0, a1, a2);
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}
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static const TCGOutOpBinary outop_shr = {
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