motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-18 23:52:14 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

target/riscv: remove cpu->cfg.ext_i

Browse source 
Create a new "i" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVI. Instances of cpu->cfg.ext_i and similar are
replaced with riscv_has_ext(env, RVI).

Remove the old "i" property and 'ext_i' from RISCVCPUConfig.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-10-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Daniel Henrique Barboza 2023-04-06 15:03:40 -03:00 • committed by Alistair Francis
parent 4b33598fbe
commit 74828eabf2
2 changed files with 7 additions and 9 deletions
Download patch file Download diff file Expand all files Collapse all files

15
target/riscv/cpu.c
View file

@ -817,13 +817,12 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
CPURISCVState *env = &cpu->env; CPURISCVState *env = &cpu->env;
/* Do some ISA extension error checking */ /* Do some ISA extension error checking */
if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && if (cpu->cfg.ext_g && !(riscv_has_ext(env, RVI) && cpu->cfg.ext_m &&
riscv_has_ext(env, RVA) && riscv_has_ext(env, RVA) &&
riscv_has_ext(env, RVF) && riscv_has_ext(env, RVF) &&
riscv_has_ext(env, RVD) && riscv_has_ext(env, RVD) &&
cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
cpu->cfg.ext_i = true;
cpu->cfg.ext_m = true; cpu->cfg.ext_m = true;
cpu->cfg.ext_icsr = true; cpu->cfg.ext_icsr = true;
cpu->cfg.ext_ifencei = true; cpu->cfg.ext_ifencei = true;
@ -832,13 +831,13 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
env->misa_ext_mask = env->misa_ext; env->misa_ext_mask = env->misa_ext;
} }
if (cpu->cfg.ext_i && cpu->cfg.ext_e) { if (riscv_has_ext(env, RVI) && cpu->cfg.ext_e) {
error_setg(errp, error_setg(errp,
"I and E extensions are incompatible"); "I and E extensions are incompatible");
return; return;
} }
if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { if (!riscv_has_ext(env, RVI) && !cpu->cfg.ext_e) {
error_setg(errp, error_setg(errp,
"Either I or E extension must be set"); "Either I or E extension must be set");
return; return;
@ -850,7 +849,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
return; return;
} }
if (cpu->cfg.ext_h && !cpu->cfg.ext_i) { if (cpu->cfg.ext_h && !riscv_has_ext(env, RVI)) {
error_setg(errp, error_setg(errp,
"H depends on an I base integer ISA with 32 x registers"); "H depends on an I base integer ISA with 32 x registers");
return; return;
@ -1148,7 +1147,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
{ {
uint32_t ext = 0; uint32_t ext = 0;
if (riscv_cpu_cfg(env)->ext_i) { if (riscv_has_ext(env, RVI)) {
ext |= RVI; ext |= RVI;
} }
if (riscv_cpu_cfg(env)->ext_e) { if (riscv_cpu_cfg(env)->ext_e) {
@ -1502,6 +1501,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
.misa_bit = RVD, .enabled = true}, .misa_bit = RVD, .enabled = true},
{.name = "f", .description = "Single-precision float point", {.name = "f", .description = "Single-precision float point",
.misa_bit = RVF, .enabled = true}, .misa_bit = RVF, .enabled = true},
{.name = "i", .description = "Base integer instruction set",
.misa_bit = RVI, .enabled = true},
}; };
static void riscv_cpu_add_misa_properties(Object *cpu_obj) static void riscv_cpu_add_misa_properties(Object *cpu_obj)
@ -1524,7 +1525,6 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
static Property riscv_cpu_extensions[] = { static Property riscv_cpu_extensions[] = {
/* Defaults for standard extensions */ /* Defaults for standard extensions */
DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true),
DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true),
@ -1644,7 +1644,6 @@ static void register_cpu_props(Object *obj)
* later on. * later on.
*/ */
if (cpu->env.misa_ext != 0) { if (cpu->env.misa_ext != 0) {
cpu->cfg.ext_i = misa_ext & RVI;
cpu->cfg.ext_e = misa_ext & RVE; cpu->cfg.ext_e = misa_ext & RVE;
cpu->cfg.ext_m = misa_ext & RVM; cpu->cfg.ext_m = misa_ext & RVM;
cpu->cfg.ext_v = misa_ext & RVV; cpu->cfg.ext_v = misa_ext & RVV;

1
target/riscv/cpu.h
View file

@ -422,7 +422,6 @@ typedef struct {
} RISCVSATPMap; } RISCVSATPMap;
struct RISCVCPUConfig { struct RISCVCPUConfig {
bool ext_i;
bool ext_e; bool ext_e;
bool ext_g; bool ext_g;
bool ext_m; bool ext_m;