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target-arm: Minimal implementation of performance counters

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Newer Linux kernels assume the existence of the performance counter
cp15 registers. Provide a minimal implementation of these registers.
We support no events. This should be compliant with the ARM ARM,
except that we don't implement the cycle counter.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2011-03-22 12:16:16 +00:00
parent b501b5e461
commit 74594c9d81
4 changed files with 184 additions and 17 deletions
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20
target-arm/translate.c
View file

@ -2472,12 +2472,28 @@ static int disas_cp_insn(CPUState *env, DisasContext *s, uint32_t insn)
return 0;
}
static int cp15_user_ok(uint32_t insn)
static int cp15_user_ok(CPUState *env, uint32_t insn)
{
int cpn = (insn >> 16) & 0xf;
int cpm = insn & 0xf;
int op = ((insn >> 5) & 7) | ((insn >> 18) & 0x38);
if (arm_feature(env, ARM_FEATURE_V7) && cpn == 9) {
/* Performance monitor registers fall into three categories:
* (a) always UNDEF in usermode
* (b) UNDEF only if PMUSERENR.EN is 0
* (c) always read OK and UNDEF on write (PMUSERENR only)
*/
if ((cpm == 12 && (op < 6)) ||
(cpm == 13 && (op < 3))) {
return env->cp15.c9_pmuserenr;
} else if (cpm == 14 && op == 0 && (insn & ARM_CP_RW_BIT)) {
/* PMUSERENR, read only */
return 1;
}
return 0;
}
if (cpn == 13 && cpm == 0) {
/* TLS register. */
if (op == 2 || (op == 3 && (insn & ARM_CP_RW_BIT)))
@ -2564,7 +2580,7 @@ static int disas_cp15_insn(CPUState *env, DisasContext *s, uint32_t insn)
/* cdp */
return 1;
}
if (IS_USER(s) && !cp15_user_ok(insn)) {
if (IS_USER(s) && !cp15_user_ok(env, insn)) {
return 1;
}