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tcg: Split out target/arch/cpu-param.h

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For all targets, into this new file move TARGET_LONG_BITS,
TARGET_PAGE_BITS, TARGET_PHYS_ADDR_SPACE_BITS,
TARGET_VIRT_ADDR_SPACE_BITS, and NB_MMU_MODES.

Include this new file from exec/cpu-defs.h.

This now removes the somewhat odd requirement that target/arch/cpu.h
defines TARGET_LONG_BITS before including exec/cpu-defs.h, so push the
bulk of the includes within target/arch/cpu.h to the top.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2019-03-22 11:51:19 -07:00
parent 79e4208506
commit 74433bf083
45 changed files with 544 additions and 333 deletions
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34
target/hppa/cpu-param.h Normal file
View file

@ -0,0 +1,34 @@
/*
* PA-RISC cpu parameters for qemu.
*
* Copyright (c) 2016 Richard Henderson <rth@twiddle.net>
* SPDX-License-Identifier: LGPL-2.0+
*/
#ifndef HPPA_CPU_PARAM_H
#define HPPA_CPU_PARAM_H 1
#ifdef TARGET_HPPA64
# define TARGET_LONG_BITS 64
# define TARGET_REGISTER_BITS 64
# define TARGET_VIRT_ADDR_SPACE_BITS 64
# define TARGET_PHYS_ADDR_SPACE_BITS 64
#elif defined(CONFIG_USER_ONLY)
# define TARGET_LONG_BITS 32
# define TARGET_REGISTER_BITS 32
# define TARGET_VIRT_ADDR_SPACE_BITS 32
# define TARGET_PHYS_ADDR_SPACE_BITS 32
#else
/*
* In order to form the GVA from space:offset,
* we need a 64-bit virtual address space.
*/
# define TARGET_LONG_BITS 64
# define TARGET_REGISTER_BITS 32
# define TARGET_VIRT_ADDR_SPACE_BITS 64
# define TARGET_PHYS_ADDR_SPACE_BITS 32
#endif
#define TARGET_PAGE_BITS 12
#define NB_MMU_MODES 5
#endif

24
target/hppa/cpu.h
View file

@ -22,25 +22,8 @@
#include "qemu-common.h"
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
#ifdef TARGET_HPPA64
#define TARGET_LONG_BITS 64
#define TARGET_VIRT_ADDR_SPACE_BITS 64
#define TARGET_REGISTER_BITS 64
#define TARGET_PHYS_ADDR_SPACE_BITS 64
#elif defined(CONFIG_USER_ONLY)
#define TARGET_LONG_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32
#define TARGET_REGISTER_BITS 32
#define TARGET_PHYS_ADDR_SPACE_BITS 32
#else
/* In order to form the GVA from space:offset,
we need a 64-bit virtual address space. */
#define TARGET_LONG_BITS 64
#define TARGET_VIRT_ADDR_SPACE_BITS 64
#define TARGET_REGISTER_BITS 32
#define TARGET_PHYS_ADDR_SPACE_BITS 32
#endif
/* PA-RISC 1.x processors have a strong memory model. */
/* ??? While we do not yet implement PA-RISC 2.0, those processors have
@ -50,12 +33,7 @@
#define CPUArchState struct CPUHPPAState
#include "exec/cpu-defs.h"
#define TARGET_PAGE_BITS 12
#define ALIGNED_ONLY
#define NB_MMU_MODES 5
#define MMU_KERNEL_IDX 0
#define MMU_USER_IDX 3
#define MMU_PHYS_IDX 4