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ppc4xx: Use Ppc4xxSdramBank in ppc4xx_sdram_banks()

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Change ppc4xx_sdram_banks() to take one Ppc4xxSdramBank array instead
of the separate arrays and adjust ppc4xx_sdram_init() and
ppc440_sdram_init() accordingly as well as machines using these.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <e3a1fea51f29779fd6a61be90a29c684f3299544.1664021647.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
This commit is contained in:
BALATON Zoltan 2022-09-24 14:27:53 +02:00 • committed by Daniel Henrique Barboza
parent 68b9a2e38d
commit 734c44ea13
8 changed files with 35 additions and 53 deletions
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15
hw/ppc/ppc440_bamboo.c
View file

@ -168,9 +168,8 @@ static void bamboo_init(MachineState *machine)
unsigned int pci_irq_nrs[4] = { 28, 27, 26, 25 };
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *isa = g_new(MemoryRegion, 1);
MemoryRegion *ram_memories = g_new(MemoryRegion, PPC440EP_SDRAM_NR_BANKS);
hwaddr ram_bases[PPC440EP_SDRAM_NR_BANKS] = {0};
hwaddr ram_sizes[PPC440EP_SDRAM_NR_BANKS] = {0};
Ppc4xxSdramBank *ram_banks = g_new0(Ppc4xxSdramBank,
PPC440EP_SDRAM_NR_BANKS);
PCIBus *pcibus;
PowerPCCPU *cpu;
CPUPPCState *env;
@ -205,13 +204,11 @@ static void bamboo_init(MachineState *machine)
qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_CINT));
/* SDRAM controller */
ppc4xx_sdram_banks(machine->ram, PPC440EP_SDRAM_NR_BANKS, ram_memories,
ram_bases, ram_sizes, ppc440ep_sdram_bank_sizes);
ppc4xx_sdram_banks(machine->ram, PPC440EP_SDRAM_NR_BANKS, ram_banks,
ppc440ep_sdram_bank_sizes);
/* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */
ppc4xx_sdram_init(env,
qdev_get_gpio_in(uicdev, 14),
PPC440EP_SDRAM_NR_BANKS, ram_memories,
ram_bases, ram_sizes);
ppc4xx_sdram_init(env, qdev_get_gpio_in(uicdev, 14),
PPC440EP_SDRAM_NR_BANKS, ram_banks);
/* Enable SDRAM memory regions, this should be done by the firmware */
ppc4xx_sdram_enable(env);