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tcg-arm: Make use of conditional availability of opcodes for divide

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We can now detect and use divide instructions at runtime, rather than
having to restrict their availability to compile-time.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson 2013-05-02 12:18:38 +01:00
parent c1a61f6c85
commit 72e1ccfc0c
2 changed files with 22 additions and 8 deletions
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16
tcg/arm/tcg-target.c
View file

@ -67,6 +67,13 @@ static const int use_armv7_instructions = 0;
#endif
#undef USE_ARMV7_INSTRUCTIONS
#ifndef use_idiv_instructions
bool use_idiv_instructions;
#endif
#ifdef CONFIG_GETAUXVAL
# include <sys/auxv.h>
#endif
#ifndef NDEBUG
static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
"%r0",
@ -2029,16 +2036,21 @@ static const TCGTargetOpDef arm_op_defs[] = {
{ INDEX_op_deposit_i32, { "r", "0", "rZ" } },
#if TCG_TARGET_HAS_div_i32
{ INDEX_op_div_i32, { "r", "r", "r" } },
{ INDEX_op_divu_i32, { "r", "r", "r" } },
#endif
{ -1 },
};
static void tcg_target_init(TCGContext *s)
{
#if defined(CONFIG_GETAUXVAL) && !defined(use_idiv_instructions)
{
unsigned long hwcap = getauxval(AT_HWCAP);
use_idiv_instructions = (hwcap & HWCAP_ARM_IDIVA) != 0;
}
#endif
tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff);
tcg_regset_set32(tcg_target_call_clobber_regs, 0,
(1 << TCG_REG_R0) |