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target/mips: introduce decodetree structure for Cavium Octeon extension

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This patch adds decodetree for Cavium Octeon extension and
an instruction set extension flag for using it in CPU models.

Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <165572672162.167724.13656301229517693806.stgit@pasha-ThinkPad-X280>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
This commit is contained in:
Pavel Dovgalyuk 2022-06-20 15:05:21 +03:00 • committed by Philippe Mathieu-Daudé
parent 8e3d85d36b
commit 72d680e408
6 changed files with 31 additions and 0 deletions
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5
target/mips/tcg/translate.c
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@ -15955,6 +15955,11 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
if (cpu_supports_isa(env, INSN_VR54XX) && decode_ext_vr54xx(ctx, ctx->opcode)) {
return;
}
#if defined(TARGET_MIPS64)
if (cpu_supports_isa(env, INSN_OCTEON) && decode_ext_octeon(ctx, ctx->opcode)) {
return;
}
#endif
/* ISA extensions */
if (ase_msa_available(env) && decode_ase_msa(ctx, ctx->opcode)) {