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target-mips: optimize gen_cp1()

Browse source 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7041 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
aurel32 2009-04-08 21:47:44 +00:00
parent 1fc7bf6ee8
commit 72c3a3ee4d
1 changed files with 5 additions and 15 deletions
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20
target-mips/translate.c
View file

@ -5578,7 +5578,7 @@ static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op,
static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs) static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
{ {
const char *opn = "cp1 move"; const char *opn = "cp1 move";
TCGv t0 = tcg_temp_local_new(); TCGv t0 = tcg_temp_new();
switch (opc) { switch (opc) {
case OPC_MFC1: case OPC_MFC1:
@ -5613,28 +5613,18 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
gen_helper_1i(ctc1, t0, fs); gen_helper_1i(ctc1, t0, fs);
opn = "ctc1"; opn = "ctc1";
break; break;
#if defined(TARGET_MIPS64)
case OPC_DMFC1: case OPC_DMFC1:
{ gen_load_fpr64(ctx, t0, fs);
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
tcg_gen_trunc_i64_tl(t0, fp0);
tcg_temp_free_i64(fp0);
}
gen_store_gpr(t0, rt); gen_store_gpr(t0, rt);
opn = "dmfc1"; opn = "dmfc1";
break; break;
case OPC_DMTC1: case OPC_DMTC1:
gen_load_gpr(t0, rt); gen_load_gpr(t0, rt);
{ gen_store_fpr64(ctx, t0, fs);
TCGv_i64 fp0 = tcg_temp_new_i64();
tcg_gen_extu_tl_i64(fp0, t0);
gen_store_fpr64(ctx, fp0, fs);
tcg_temp_free_i64(fp0);
}
opn = "dmtc1"; opn = "dmtc1";
break; break;
#endif
case OPC_MFHC1: case OPC_MFHC1:
{ {
TCGv_i32 fp0 = tcg_temp_new_i32(); TCGv_i32 fp0 = tcg_temp_new_i32();