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target/arm: Mark FTSMUL, FTMAD, FADDA as non-streaming

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Mark these as a non-streaming instructions, which should trap
if full a64 support is not enabled in streaming mode.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2022-07-08 20:45:03 +05:30 • committed by Peter Maydell
parent 4464ee3634
commit 7272e98a74
2 changed files with 11 additions and 7 deletions
Download patch file Download diff file Expand all files Collapse all files

3
target/arm/sme-fa64.decode
View file

@ -59,9 +59,6 @@ FAIL 0001 1110 0111 1110 0000 00-- ---- ---- # FJCVTZS
# --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register (register offset) # --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register (register offset)
# --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register (scaled imm) # --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register (scaled imm)
FAIL 0110 0101 --0- ---- 0000 11-- ---- ---- # FTSMUL
FAIL 0110 0101 --01 0--- 100- ---- ---- ---- # FTMAD
FAIL 0110 0101 --01 1--- 001- ---- ---- ---- # FADDA
FAIL 0100 0101 --0- ---- 1001 10-- ---- ---- # SMMLA, UMMLA, USMMLA FAIL 0100 0101 --0- ---- 1001 10-- ---- ---- # SMMLA, UMMLA, USMMLA
FAIL 0100 0101 --1- ---- 1--- ---- ---- ---- # SVE2 string/histo/crypto instructions FAIL 0100 0101 --1- ---- 1--- ---- ---- ---- # SVE2 string/histo/crypto instructions
FAIL 1000 010- -00- ---- 10-- ---- ---- ---- # SVE2 32-bit gather NT load (vector+scalar) FAIL 1000 010- -00- ---- 10-- ---- ---- ---- # SVE2 32-bit gather NT load (vector+scalar)

15
target/arm/translate-sve.c
View file

@ -3861,9 +3861,9 @@ static gen_helper_gvec_3_ptr * const ftmad_fns[4] = {
NULL, gen_helper_sve_ftmad_h, NULL, gen_helper_sve_ftmad_h,
gen_helper_sve_ftmad_s, gen_helper_sve_ftmad_d, gen_helper_sve_ftmad_s, gen_helper_sve_ftmad_d,
}; };
TRANS_FEAT(FTMAD, aa64_sve, gen_gvec_fpst_zzz, TRANS_FEAT_NONSTREAMING(FTMAD, aa64_sve, gen_gvec_fpst_zzz,
ftmad_fns[a->esz], a->rd, a->rn, a->rm, a->imm, ftmad_fns[a->esz], a->rd, a->rn, a->rm, a->imm,
a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR) a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR)
/* /*
*** SVE Floating Point Accumulating Reduction Group *** SVE Floating Point Accumulating Reduction Group
@ -3886,6 +3886,7 @@ static bool trans_FADDA(DisasContext *s, arg_rprr_esz *a)
if (a->esz == 0 || !dc_isar_feature(aa64_sve, s)) { if (a->esz == 0 || !dc_isar_feature(aa64_sve, s)) {
return false; return false;
} }
s->is_nonstreaming = true;
if (!sve_access_check(s)) { if (!sve_access_check(s)) {
return true; return true;
} }
@ -3923,12 +3924,18 @@ static bool trans_FADDA(DisasContext *s, arg_rprr_esz *a)
DO_FP3(FADD_zzz, fadd) DO_FP3(FADD_zzz, fadd)
DO_FP3(FSUB_zzz, fsub) DO_FP3(FSUB_zzz, fsub)
DO_FP3(FMUL_zzz, fmul) DO_FP3(FMUL_zzz, fmul)
DO_FP3(FTSMUL, ftsmul)
DO_FP3(FRECPS, recps) DO_FP3(FRECPS, recps)
DO_FP3(FRSQRTS, rsqrts) DO_FP3(FRSQRTS, rsqrts)
#undef DO_FP3 #undef DO_FP3
static gen_helper_gvec_3_ptr * const ftsmul_fns[4] = {
NULL, gen_helper_gvec_ftsmul_h,
gen_helper_gvec_ftsmul_s, gen_helper_gvec_ftsmul_d
};
TRANS_FEAT_NONSTREAMING(FTSMUL, aa64_sve, gen_gvec_fpst_arg_zzz,
ftsmul_fns[a->esz], a, 0)
/* /*
*** SVE Floating Point Arithmetic - Predicated Group *** SVE Floating Point Arithmetic - Predicated Group
*/ */