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target/arm: Fix decode of fp16 vector fabs, fneg, fsqrt

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These opcodes are only supported as vector operations,
not as advsimd scalar.  Set only_in_vector, and remove
the unreachable implementation of scalar fneg.

Reported-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20241211163036.2297116-24-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2024-12-11 10:29:50 -06:00 • committed by Peter Maydell
parent cc0db9dea0
commit 7261f2a7a7
1 changed files with 3 additions and 3 deletions
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6
target/arm/tcg/translate-a64.c
View file

@ -10816,10 +10816,13 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
break;
case 0x2f: /* FABS */
case 0x6f: /* FNEG */
only_in_vector = true;
need_fpst = false;
break;
case 0x7d: /* FRSQRTE */
break;
case 0x7f: /* FSQRT (vector) */
only_in_vector = true;
break;
default:
unallocated_encoding(s);
@ -10877,9 +10880,6 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
case 0x7b: /* FCVTZU */
gen_helper_advsimd_f16touinth(tcg_res, tcg_op, tcg_fpstatus);
break;
case 0x6f: /* FNEG */
tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
break;
case 0x7d: /* FRSQRTE */
gen_helper_rsqrte_f16(tcg_res, tcg_op, tcg_fpstatus);
break;