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hw/net/xilinx_ethlite: Map RX_CTRL as MMIO

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Declare RX registers as MMIO region, split it out
of the current mixed RAM/MMIO region.
The memory flat view becomes:

  (qemu) info mtree -f
  FlatView #0
   Root memory region: system
    0000000081000000-00000000810007e3 (prio 0, i/o): xlnx.xps-ethernetlite
    00000000810007e4-00000000810007f3 (prio 0, i/o): ethlite.mdio
    00000000810007f4-00000000810017fb (prio 0, i/o): xlnx.xps-ethernetlite @00000000000007f4
    00000000810017fc-00000000810017ff (prio 0, i/o): ethlite.rx[0]io
    0000000081001800-0000000081001ffb (prio 0, i/o): xlnx.xps-ethernetlite @0000000000001800
    0000000081001ffc-0000000081001fff (prio 0, i/o): ethlite.rx[1]io

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20241112181044.92193-16-philmd@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé 2024-11-09 20:03:00 +01:00
parent a375066991
commit 7229496206
1 changed files with 67 additions and 15 deletions
Download patch file Download diff file Expand all files Collapse all files

82
hw/net/xilinx_ethlite.c
View file

@ -49,11 +49,16 @@
#define R_TX_CTRL1 (0x0ffc / 4)
#define R_RX_BUF0 (0x1000 / 4)
#define R_RX_CTRL0 (0x17fc / 4)
#define A_RX_BASE0 0x17fc
#define R_RX_BUF1 (0x1800 / 4)
#define R_RX_CTRL1 (0x1ffc / 4)
#define A_RX_BASE1 0x1ffc
#define R_MAX (0x2000 / 4)
enum {
RX_CTRL = 0,
RX_MAX
};
#define GIE_GIE 0x80000000
#define CTRL_I 0x8
@ -61,6 +66,8 @@
#define CTRL_S 0x1
typedef struct XlnxXpsEthLitePort {
MemoryRegion rxio;
struct {
uint32_t tx_len;
uint32_t tx_gie;
@ -118,6 +125,55 @@ static void *rxbuf_ptr(XlnxXpsEthLite *s, unsigned port_index)
return &s->regs[rxbase + R_RX_BUF0];
}
static uint64_t port_rx_read(void *opaque, hwaddr addr, unsigned int size)
{
XlnxXpsEthLite *s = opaque;
unsigned port_index = addr_to_port_index(addr);
uint32_t r = 0;
switch (addr >> 2) {
case RX_CTRL:
r = s->port[port_index].reg.rx_ctrl;
break;
default:
g_assert_not_reached();
}
return r;
}
static void port_rx_write(void *opaque, hwaddr addr, uint64_t value,
unsigned int size)
{
XlnxXpsEthLite *s = opaque;
unsigned port_index = addr_to_port_index(addr);
switch (addr >> 2) {
case RX_CTRL:
if (!(value & CTRL_S)) {
qemu_flush_queued_packets(qemu_get_queue(s->nic));
}
s->port[port_index].reg.rx_ctrl = value;
break;
default:
g_assert_not_reached();
}
}
static const MemoryRegionOps eth_portrx_ops = {
.read = port_rx_read,
.write = port_rx_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.impl = {
.min_access_size = 4,
.max_access_size = 4,
},
.valid = {
.min_access_size = 4,
.max_access_size = 4,
},
};
static uint64_t
eth_read(void *opaque, hwaddr addr, unsigned int size)
{
@ -143,11 +199,6 @@ eth_read(void *opaque, hwaddr addr, unsigned int size)
r = s->port[port_index].reg.tx_ctrl;
break;
case R_RX_CTRL1:
case R_RX_CTRL0:
r = s->port[port_index].reg.rx_ctrl;
break;
default:
r = tswap32(s->regs[addr]);
break;
@ -188,14 +239,6 @@ eth_write(void *opaque, hwaddr addr,
break;
/* Keep these native. */
case R_RX_CTRL0:
case R_RX_CTRL1:
if (!(value & CTRL_S)) {
qemu_flush_queued_packets(qemu_get_queue(s->nic));
}
s->port[port_index].reg.rx_ctrl = value;
break;
case R_TX_LEN0:
case R_TX_LEN1:
s->port[port_index].reg.tx_len = value;
@ -288,6 +331,15 @@ static void xilinx_ethlite_realize(DeviceState *dev, Error **errp)
memory_region_add_subregion(&s->mmio, A_MDIO_BASE,
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->mdio), 0));
for (unsigned i = 0; i < 2; i++) {
memory_region_init_io(&s->port[i].rxio, OBJECT(dev),
&eth_portrx_ops, s,
i ? "ethlite.rx[1]io" : "ethlite.rx[0]io",
4 * RX_MAX);
memory_region_add_subregion(&s->mmio, i ? A_RX_BASE1 : A_RX_BASE0,
&s->port[i].rxio);
}
qemu_macaddr_default_if_unset(&s->conf.macaddr);
s->nic = qemu_new_nic(&net_xilinx_ethlite_info, &s->conf,
object_get_typename(OBJECT(dev)), dev->id,