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target/ppc: Cleanup HPTE accessors for 64-bit hash MMU
Accesses to the hashed page table (HPT) are complicated by the fact that
the HPT could be in one of three places:
1) Within guest memory - when we're emulating a full guest CPU at the
hardware level (e.g. powernv, mac99, g3beige)
2) Within qemu, but outside guest memory - when we're emulating user and
supervisor instructions within TCG, but instead of emulating
the CPU's hypervisor mode, we just emulate a hypervisor's behaviour
(pseries in TCG or KVM-PR)
3) Within the host kernel - a pseries machine using KVM-HV
acceleration. Mostly accesses to the HPT are handled by KVM,
but there are a few cases where qemu needs to access it via a
special fd for the purpose.
In order to batch accesses to the fd in case (3), we use a somewhat awkward
ppc_hash64_start_access() / ppc_hash64_stop_access() pair, which for case
(3) reads / releases several HPTEs from the kernel as a batch (usually a
whole PTEG). For cases (1) & (2) it just returns an address value. The
actual HPTE load helpers then need to interpret the returned token
differently in the 3 cases.
This patch keeps the same basic structure, but simplfiies the details.
First start_access() / stop_access() are renamed to map_hptes() and
unmap_hptes() to make their operation more obvious. Second, map_hptes()
now always returns a qemu pointer, which can always be used in the same way
by the load_hpte() helpers. In case (1) it comes from address_space_map()
in case (2) directly from qemu's HPT buffer and in case (3) from a
temporary buffer read from the KVM fd.
While we're at it, make things a bit more consistent in terms of types and
variable names: avoid variables named 'index' (it shadows index(3) which
can lead to confusing results), use 'hwaddr ptex' for HPTE indices and
uint64_t for each of the HPTE words, use ptex throughout the call stack
instead of pte_offset in some places (we still need that at the bottom
layer, but nowhere else).
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
David Gibson
parent
7d6250e3d1
commit
7222b94a83
4 changed files with 94 additions and 103 deletions
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@ -27,6 +27,7 @@
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#include "kvm_ppc.h"
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#include "mmu-hash64.h"
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#include "exec/log.h"
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#include "hw/hw.h"
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//#define DEBUG_SLB
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@ -431,35 +432,43 @@ static int ppc_hash64_amr_prot(PowerPCCPU *cpu, ppc_hash_pte64_t pte)
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return prot;
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}
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uint64_t ppc_hash64_start_access(PowerPCCPU *cpu, target_ulong pte_index)
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const ppc_hash_pte64_t *ppc_hash64_map_hptes(PowerPCCPU *cpu,
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hwaddr ptex, int n)
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{
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uint64_t token = 0;
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hwaddr pte_offset;
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ppc_hash_pte64_t *hptes = NULL;
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hwaddr pte_offset = ptex * HASH_PTE_SIZE_64;
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pte_offset = pte_index * HASH_PTE_SIZE_64;
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if (cpu->env.external_htab == MMU_HASH64_KVM_MANAGED_HPT) {
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ppc_hash_pte64_t *pteg = g_malloc(HASH_PTEG_SIZE_64);
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/*
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* HTAB is controlled by KVM. Fetch the PTEG into a new buffer.
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* HTAB is controlled by KVM. Fetch into temporary buffer
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*/
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kvmppc_read_hptes(pteg, pte_index, HPTES_PER_GROUP);
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token = (uint64_t)(uintptr_t)pteg;
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hptes = g_malloc(HASH_PTEG_SIZE_64);
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kvmppc_read_hptes(hptes, ptex, n);
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} else if (cpu->env.external_htab) {
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/*
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* HTAB is controlled by QEMU. Just point to the internally
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* accessible PTEG.
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*/
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token = (uint64_t)(uintptr_t) cpu->env.external_htab + pte_offset;
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hptes = (ppc_hash_pte64_t *)(cpu->env.external_htab + pte_offset);
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} else if (cpu->env.htab_base) {
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token = cpu->env.htab_base + pte_offset;
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hwaddr plen = n * HASH_PTE_SIZE_64;
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hptes = address_space_map(CPU(cpu)->as, cpu->env.htab_base + pte_offset,
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&plen, false);
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if (plen < (n * HASH_PTE_SIZE_64)) {
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hw_error("%s: Unable to map all requested HPTEs\n", __func__);
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}
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}
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return token;
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return hptes;
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}
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void ppc_hash64_stop_access(PowerPCCPU *cpu, uint64_t token)
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void ppc_hash64_unmap_hptes(PowerPCCPU *cpu, const ppc_hash_pte64_t *hptes,
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hwaddr ptex, int n)
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{
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if (cpu->env.external_htab == MMU_HASH64_KVM_MANAGED_HPT) {
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g_free((void *)token);
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g_free((void *)hptes);
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} else if (!cpu->env.external_htab) {
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address_space_unmap(CPU(cpu)->as, (void *)hptes, n * HASH_PTE_SIZE_64,
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false, n * HASH_PTE_SIZE_64);
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}
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}
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@ -507,18 +516,18 @@ static hwaddr ppc_hash64_pteg_search(PowerPCCPU *cpu, hwaddr hash,
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{
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CPUPPCState *env = &cpu->env;
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int i;
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uint64_t token;
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const ppc_hash_pte64_t *pteg;
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target_ulong pte0, pte1;
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target_ulong pte_index;
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target_ulong ptex;
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pte_index = (hash & env->htab_mask) * HPTES_PER_GROUP;
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token = ppc_hash64_start_access(cpu, pte_index);
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if (!token) {
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ptex = (hash & env->htab_mask) * HPTES_PER_GROUP;
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pteg = ppc_hash64_map_hptes(cpu, ptex, HPTES_PER_GROUP);
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if (!pteg) {
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return -1;
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}
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for (i = 0; i < HPTES_PER_GROUP; i++) {
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pte0 = ppc_hash64_load_hpte0(cpu, token, i);
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pte1 = ppc_hash64_load_hpte1(cpu, token, i);
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pte0 = ppc_hash64_hpte0(cpu, pteg, i);
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pte1 = ppc_hash64_hpte1(cpu, pteg, i);
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/* This compares V, B, H (secondary) and the AVPN */
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if (HPTE64_V_COMPARE(pte0, ptem)) {
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@ -538,11 +547,11 @@ static hwaddr ppc_hash64_pteg_search(PowerPCCPU *cpu, hwaddr hash,
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*/
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pte->pte0 = pte0;
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pte->pte1 = pte1;
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ppc_hash64_stop_access(cpu, token);
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return (pte_index + i) * HASH_PTE_SIZE_64;
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ppc_hash64_unmap_hptes(cpu, pteg, ptex, HPTES_PER_GROUP);
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return ptex + i;
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}
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}
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ppc_hash64_stop_access(cpu, token);
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ppc_hash64_unmap_hptes(cpu, pteg, ptex, HPTES_PER_GROUP);
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/*
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* We didn't find a valid entry.
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*/
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@ -554,8 +563,7 @@ static hwaddr ppc_hash64_htab_lookup(PowerPCCPU *cpu,
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ppc_hash_pte64_t *pte, unsigned *pshift)
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{
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CPUPPCState *env = &cpu->env;
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hwaddr pte_offset;
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hwaddr hash;
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hwaddr hash, ptex;
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uint64_t vsid, epnmask, epn, ptem;
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const struct ppc_one_seg_page_size *sps = slb->sps;
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@ -598,9 +606,9 @@ static hwaddr ppc_hash64_htab_lookup(PowerPCCPU *cpu,
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" vsid=" TARGET_FMT_lx " ptem=" TARGET_FMT_lx
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" hash=" TARGET_FMT_plx "\n",
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env->htab_base, env->htab_mask, vsid, ptem, hash);
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pte_offset = ppc_hash64_pteg_search(cpu, hash, sps, ptem, pte, pshift);
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ptex = ppc_hash64_pteg_search(cpu, hash, sps, ptem, pte, pshift);
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if (pte_offset == -1) {
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if (ptex == -1) {
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/* Secondary PTEG lookup */
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ptem |= HPTE64_V_SECONDARY;
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qemu_log_mask(CPU_LOG_MMU,
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@ -609,10 +617,10 @@ static hwaddr ppc_hash64_htab_lookup(PowerPCCPU *cpu,
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" hash=" TARGET_FMT_plx "\n", env->htab_base,
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env->htab_mask, vsid, ptem, ~hash);
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pte_offset = ppc_hash64_pteg_search(cpu, ~hash, sps, ptem, pte, pshift);
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ptex = ppc_hash64_pteg_search(cpu, ~hash, sps, ptem, pte, pshift);
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}
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return pte_offset;
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return ptex;
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}
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unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
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@ -710,7 +718,7 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,
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CPUPPCState *env = &cpu->env;
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ppc_slb_t *slb;
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unsigned apshift;
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hwaddr pte_offset;
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hwaddr ptex;
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ppc_hash_pte64_t pte;
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int pp_prot, amr_prot, prot;
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uint64_t new_pte1, dsisr;
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@ -794,8 +802,8 @@ skip_slb_search:
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}
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/* 4. Locate the PTE in the hash table */
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pte_offset = ppc_hash64_htab_lookup(cpu, slb, eaddr, &pte, &apshift);
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if (pte_offset == -1) {
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ptex = ppc_hash64_htab_lookup(cpu, slb, eaddr, &pte, &apshift);
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if (ptex == -1) {
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dsisr = 0x40000000;
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if (rwx == 2) {
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ppc_hash64_set_isi(cs, env, dsisr);
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@ -808,7 +816,7 @@ skip_slb_search:
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return 1;
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}
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qemu_log_mask(CPU_LOG_MMU,
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"found PTE at offset %08" HWADDR_PRIx "\n", pte_offset);
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"found PTE at index %08" HWADDR_PRIx "\n", ptex);
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/* 5. Check access permissions */
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@ -851,8 +859,7 @@ skip_slb_search:
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}
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if (new_pte1 != pte.pte1) {
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ppc_hash64_store_hpte(cpu, pte_offset / HASH_PTE_SIZE_64,
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pte.pte0, new_pte1);
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ppc_hash64_store_hpte(cpu, ptex, pte.pte0, new_pte1);
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}
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/* 7. Determine the real address from the PTE */
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@ -869,7 +876,7 @@ hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr)
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{
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CPUPPCState *env = &cpu->env;
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ppc_slb_t *slb;
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hwaddr pte_offset, raddr;
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hwaddr ptex, raddr;
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ppc_hash_pte64_t pte;
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unsigned apshift;
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@ -902,8 +909,8 @@ hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr)
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}
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}
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pte_offset = ppc_hash64_htab_lookup(cpu, slb, addr, &pte, &apshift);
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if (pte_offset == -1) {
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ptex = ppc_hash64_htab_lookup(cpu, slb, addr, &pte, &apshift);
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if (ptex == -1) {
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return -1;
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}
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@ -911,30 +918,28 @@ hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr)
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& TARGET_PAGE_MASK;
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}
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void ppc_hash64_store_hpte(PowerPCCPU *cpu,
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target_ulong pte_index,
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target_ulong pte0, target_ulong pte1)
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void ppc_hash64_store_hpte(PowerPCCPU *cpu, hwaddr ptex,
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uint64_t pte0, uint64_t pte1)
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{
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CPUPPCState *env = &cpu->env;
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hwaddr offset = ptex * HASH_PTE_SIZE_64;
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if (env->external_htab == MMU_HASH64_KVM_MANAGED_HPT) {
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kvmppc_write_hpte(pte_index, pte0, pte1);
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kvmppc_write_hpte(ptex, pte0, pte1);
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return;
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}
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pte_index *= HASH_PTE_SIZE_64;
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if (env->external_htab) {
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stq_p(env->external_htab + pte_index, pte0);
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stq_p(env->external_htab + pte_index + HASH_PTE_SIZE_64 / 2, pte1);
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stq_p(env->external_htab + offset, pte0);
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stq_p(env->external_htab + offset + HASH_PTE_SIZE_64 / 2, pte1);
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} else {
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stq_phys(CPU(cpu)->as, env->htab_base + pte_index, pte0);
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stq_phys(CPU(cpu)->as, env->htab_base + offset, pte0);
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stq_phys(CPU(cpu)->as,
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env->htab_base + pte_index + HASH_PTE_SIZE_64 / 2, pte1);
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env->htab_base + offset + HASH_PTE_SIZE_64 / 2, pte1);
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}
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}
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void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu,
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target_ulong pte_index,
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void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu, target_ulong ptex,
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target_ulong pte0, target_ulong pte1)
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{
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/*
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