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target/ppc: Add function to get protection key for hash32 MMU

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Add a function to get key bit from SR and use it instead of open coded
version.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
This commit is contained in:
BALATON Zoltan 2024-05-27 01:12:54 +02:00 • committed by Nicholas Piggin
parent cab21e2ecb
commit 719a1da19e
3 changed files with 12 additions and 5 deletions
Download patch file Download diff file Expand all files Collapse all files

9
target/ppc/mmu-hash32.c
View file

@ -42,7 +42,7 @@ static int ppc_hash32_pte_prot(int mmu_idx,
{ {
unsigned pp, key; unsigned pp, key;
key = !!(mmuidx_pr(mmu_idx) ? (sr & SR32_KP) : (sr & SR32_KS)); key = ppc_hash32_key(mmuidx_pr(mmu_idx), sr);
pp = pte.pte1 & HPTE32_R_PP; pp = pte.pte1 & HPTE32_R_PP;
return ppc_hash32_prot(key, pp, !!(sr & SR32_NX)); return ppc_hash32_prot(key, pp, !!(sr & SR32_NX));
@ -145,7 +145,6 @@ static bool ppc_hash32_direct_store(PowerPCCPU *cpu, target_ulong sr,
{ {
CPUState *cs = CPU(cpu); CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env; CPUPPCState *env = &cpu->env;
int key = !!(mmuidx_pr(mmu_idx) ? (sr & SR32_KP) : (sr & SR32_KS));
qemu_log_mask(CPU_LOG_MMU, "direct store...\n"); qemu_log_mask(CPU_LOG_MMU, "direct store...\n");
@ -206,7 +205,11 @@ static bool ppc_hash32_direct_store(PowerPCCPU *cpu, target_ulong sr,
cpu_abort(cs, "ERROR: insn should not need address translation\n"); cpu_abort(cs, "ERROR: insn should not need address translation\n");
} }
*prot = key ? PAGE_READ | PAGE_WRITE : PAGE_READ; if (ppc_hash32_key(mmuidx_pr(mmu_idx), sr)) {
*prot = PAGE_READ | PAGE_WRITE;
} else {
*prot = PAGE_READ;
}
if (check_prot_access_type(*prot, access_type)) { if (check_prot_access_type(*prot, access_type)) {
*raddr = eaddr; *raddr = eaddr;
return true; return true;

5
target/ppc/mmu-hash32.h
View file

@ -102,6 +102,11 @@ static inline void ppc_hash32_store_hpte1(PowerPCCPU *cpu,
stl_phys(CPU(cpu)->as, base + pte_offset + HASH_PTE_SIZE_32 / 2, pte1); stl_phys(CPU(cpu)->as, base + pte_offset + HASH_PTE_SIZE_32 / 2, pte1);
} }
static inline bool ppc_hash32_key(bool pr, target_ulong sr)
{
return pr ? (sr & SR32_KP) : (sr & SR32_KS);
}
static inline int ppc_hash32_prot(bool key, int pp, bool nx) static inline int ppc_hash32_prot(bool key, int pp, bool nx)
{ {
int prot; int prot;

3
target/ppc/mmu_common.c
View file

@ -310,8 +310,7 @@ static int mmu6xx_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
pr = FIELD_EX64(env->msr, MSR, PR); pr = FIELD_EX64(env->msr, MSR, PR);
sr = env->sr[eaddr >> 28]; sr = env->sr[eaddr >> 28];
ctx->key = (((sr & 0x20000000) && pr) || ctx->key = ppc_hash32_key(pr, sr);
((sr & 0x40000000) && !pr)) ? 1 : 0;
ds = sr & SR32_T; ds = sr & SR32_T;
nx = sr & SR32_NX; nx = sr & SR32_NX;
vsid = sr & SR32_VSID; vsid = sr & SR32_VSID;