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https://github.com/Motorhead1991/qemu.git
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tcg/arm: Introduce prepare_host_addr
Merge tcg_out_tlb_load, add_qemu_ldst_label, and some code that lived in both tcg_out_qemu_ld and tcg_out_qemu_st into one function that returns HostAddress and TCGLabelQemuLdst structures. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
1e612dd66a
commit
7131d3cf72
1 changed files with 159 additions and 192 deletions
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@ -1434,125 +1434,6 @@ static TCGReg tcg_out_arg_reg64(TCGContext *s, TCGReg argreg,
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}
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}
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}
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}
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#define TLB_SHIFT (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS)
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/* We expect to use an 9-bit sign-magnitude negative offset from ENV. */
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QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
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QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -256);
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/* These offsets are built into the LDRD below. */
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QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) != 0);
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QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) != 4);
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/* Load and compare a TLB entry, leaving the flags set. Returns the register
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containing the addend of the tlb entry. Clobbers R0, R1, R2, TMP. */
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static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi,
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MemOp opc, int mem_index, bool is_load)
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{
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int cmp_off = (is_load ? offsetof(CPUTLBEntry, addr_read)
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: offsetof(CPUTLBEntry, addr_write));
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int fast_off = TLB_MASK_TABLE_OFS(mem_index);
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unsigned s_mask = (1 << (opc & MO_SIZE)) - 1;
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unsigned a_mask = (1 << get_alignment_bits(opc)) - 1;
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TCGReg t_addr;
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/* Load env_tlb(env)->f[mmu_idx].{mask,table} into {r0,r1}. */
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tcg_out_ldrd_8(s, COND_AL, TCG_REG_R0, TCG_AREG0, fast_off);
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/* Extract the tlb index from the address into R0. */
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tcg_out_dat_reg(s, COND_AL, ARITH_AND, TCG_REG_R0, TCG_REG_R0, addrlo,
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SHIFT_IMM_LSR(TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS));
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/*
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* Add the tlb_table pointer, creating the CPUTLBEntry address in R1.
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* Load the tlb comparator into R2/R3 and the fast path addend into R1.
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*/
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if (cmp_off == 0) {
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if (TARGET_LONG_BITS == 64) {
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tcg_out_ldrd_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R0);
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} else {
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tcg_out_ld32_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R0);
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}
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} else {
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tcg_out_dat_reg(s, COND_AL, ARITH_ADD,
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TCG_REG_R1, TCG_REG_R1, TCG_REG_R0, 0);
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if (TARGET_LONG_BITS == 64) {
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tcg_out_ldrd_8(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off);
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} else {
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tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off);
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}
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}
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/* Load the tlb addend. */
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tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R1,
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offsetof(CPUTLBEntry, addend));
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/*
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* Check alignment, check comparators.
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* Do this in 2-4 insns. Use MOVW for v7, if possible,
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* to reduce the number of sequential conditional instructions.
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* Almost all guests have at least 4k pages, which means that we need
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* to clear at least 9 bits even for an 8-byte memory, which means it
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* isn't worth checking for an immediate operand for BIC.
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*
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* For unaligned accesses, test the page of the last unit of alignment.
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* This leaves the least significant alignment bits unchanged, and of
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* course must be zero.
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*/
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t_addr = addrlo;
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if (a_mask < s_mask) {
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t_addr = TCG_REG_R0;
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tcg_out_dat_imm(s, COND_AL, ARITH_ADD, t_addr,
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addrlo, s_mask - a_mask);
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}
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if (use_armv7_instructions && TARGET_PAGE_BITS <= 16) {
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tcg_out_movi32(s, COND_AL, TCG_REG_TMP, ~(TARGET_PAGE_MASK | a_mask));
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tcg_out_dat_reg(s, COND_AL, ARITH_BIC, TCG_REG_TMP,
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t_addr, TCG_REG_TMP, 0);
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tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R2, TCG_REG_TMP, 0);
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} else {
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if (a_mask) {
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tcg_debug_assert(a_mask <= 0xff);
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tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, a_mask);
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}
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tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, t_addr,
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SHIFT_IMM_LSR(TARGET_PAGE_BITS));
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tcg_out_dat_reg(s, (a_mask ? COND_EQ : COND_AL), ARITH_CMP,
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0, TCG_REG_R2, TCG_REG_TMP,
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SHIFT_IMM_LSL(TARGET_PAGE_BITS));
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}
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if (TARGET_LONG_BITS == 64) {
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tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, TCG_REG_R3, addrhi, 0);
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}
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return TCG_REG_R1;
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}
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/* Record the context of a call to the out of line helper code for the slow
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path for a load or store, so that we can later generate the correct
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helper code. */
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static void add_qemu_ldst_label(TCGContext *s, bool is_ld,
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MemOpIdx oi, TCGType type,
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TCGReg datalo, TCGReg datahi,
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TCGReg addrlo, TCGReg addrhi,
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tcg_insn_unit *raddr,
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tcg_insn_unit *label_ptr)
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{
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TCGLabelQemuLdst *label = new_ldst_label(s);
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label->is_ld = is_ld;
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label->oi = oi;
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label->type = type;
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label->datalo_reg = datalo;
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label->datahi_reg = datahi;
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label->addrlo_reg = addrlo;
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label->addrhi_reg = addrhi;
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label->raddr = tcg_splitwx_to_rx(raddr);
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label->label_ptr[0] = label_ptr;
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}
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static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
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static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
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{
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{
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TCGReg argreg;
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TCGReg argreg;
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@ -1636,29 +1517,6 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
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return true;
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return true;
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}
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}
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#else
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#else
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static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addrlo,
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TCGReg addrhi, unsigned a_bits)
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{
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unsigned a_mask = (1 << a_bits) - 1;
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TCGLabelQemuLdst *label = new_ldst_label(s);
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label->is_ld = is_ld;
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label->addrlo_reg = addrlo;
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label->addrhi_reg = addrhi;
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/* We are expecting a_bits to max out at 7, and can easily support 8. */
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tcg_debug_assert(a_mask <= 0xff);
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/* tst addr, #mask */
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tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, a_mask);
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/* blne slow_path */
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label->label_ptr[0] = s->code_ptr;
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tcg_out_bl_imm(s, COND_NE, 0);
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label->raddr = tcg_splitwx_to_rx(s->code_ptr);
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}
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static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l)
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static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l)
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{
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{
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if (!reloc_pc24(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) {
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if (!reloc_pc24(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) {
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@ -1703,6 +1561,134 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
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}
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}
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#endif /* SOFTMMU */
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#endif /* SOFTMMU */
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static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
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TCGReg addrlo, TCGReg addrhi,
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MemOpIdx oi, bool is_ld)
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{
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TCGLabelQemuLdst *ldst = NULL;
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MemOp opc = get_memop(oi);
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MemOp a_bits = get_alignment_bits(opc);
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unsigned a_mask = (1 << a_bits) - 1;
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#ifdef CONFIG_SOFTMMU
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int mem_index = get_mmuidx(oi);
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int cmp_off = is_ld ? offsetof(CPUTLBEntry, addr_read)
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: offsetof(CPUTLBEntry, addr_write);
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int fast_off = TLB_MASK_TABLE_OFS(mem_index);
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unsigned s_mask = (1 << (opc & MO_SIZE)) - 1;
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TCGReg t_addr;
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ldst = new_ldst_label(s);
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ldst->is_ld = is_ld;
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ldst->oi = oi;
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ldst->addrlo_reg = addrlo;
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ldst->addrhi_reg = addrhi;
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/* Load env_tlb(env)->f[mmu_idx].{mask,table} into {r0,r1}. */
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QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
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QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -256);
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QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) != 0);
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QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) != 4);
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tcg_out_ldrd_8(s, COND_AL, TCG_REG_R0, TCG_AREG0, fast_off);
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/* Extract the tlb index from the address into R0. */
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tcg_out_dat_reg(s, COND_AL, ARITH_AND, TCG_REG_R0, TCG_REG_R0, addrlo,
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SHIFT_IMM_LSR(TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS));
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/*
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* Add the tlb_table pointer, creating the CPUTLBEntry address in R1.
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* Load the tlb comparator into R2/R3 and the fast path addend into R1.
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*/
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if (cmp_off == 0) {
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if (TARGET_LONG_BITS == 64) {
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tcg_out_ldrd_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R0);
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} else {
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tcg_out_ld32_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R0);
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}
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} else {
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tcg_out_dat_reg(s, COND_AL, ARITH_ADD,
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TCG_REG_R1, TCG_REG_R1, TCG_REG_R0, 0);
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if (TARGET_LONG_BITS == 64) {
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tcg_out_ldrd_8(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off);
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} else {
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tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off);
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}
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}
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/* Load the tlb addend. */
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tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R1,
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offsetof(CPUTLBEntry, addend));
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/*
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* Check alignment, check comparators.
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* Do this in 2-4 insns. Use MOVW for v7, if possible,
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* to reduce the number of sequential conditional instructions.
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* Almost all guests have at least 4k pages, which means that we need
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* to clear at least 9 bits even for an 8-byte memory, which means it
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* isn't worth checking for an immediate operand for BIC.
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*
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* For unaligned accesses, test the page of the last unit of alignment.
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* This leaves the least significant alignment bits unchanged, and of
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* course must be zero.
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*/
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t_addr = addrlo;
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if (a_mask < s_mask) {
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t_addr = TCG_REG_R0;
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tcg_out_dat_imm(s, COND_AL, ARITH_ADD, t_addr,
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addrlo, s_mask - a_mask);
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}
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if (use_armv7_instructions && TARGET_PAGE_BITS <= 16) {
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tcg_out_movi32(s, COND_AL, TCG_REG_TMP, ~(TARGET_PAGE_MASK | a_mask));
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tcg_out_dat_reg(s, COND_AL, ARITH_BIC, TCG_REG_TMP,
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t_addr, TCG_REG_TMP, 0);
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tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R2, TCG_REG_TMP, 0);
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} else {
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if (a_mask) {
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tcg_debug_assert(a_mask <= 0xff);
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tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, a_mask);
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}
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tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, t_addr,
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SHIFT_IMM_LSR(TARGET_PAGE_BITS));
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tcg_out_dat_reg(s, (a_mask ? COND_EQ : COND_AL), ARITH_CMP,
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0, TCG_REG_R2, TCG_REG_TMP,
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SHIFT_IMM_LSL(TARGET_PAGE_BITS));
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}
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if (TARGET_LONG_BITS == 64) {
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tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, TCG_REG_R3, addrhi, 0);
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}
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*h = (HostAddress){
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.cond = COND_AL,
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.base = addrlo,
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.index = TCG_REG_R1,
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.index_scratch = true,
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};
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#else
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if (a_mask) {
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ldst = new_ldst_label(s);
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ldst->is_ld = is_ld;
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ldst->oi = oi;
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ldst->addrlo_reg = addrlo;
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ldst->addrhi_reg = addrhi;
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/* We are expecting a_bits to max out at 7 */
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tcg_debug_assert(a_mask <= 0xff);
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/* tst addr, #mask */
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tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, a_mask);
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}
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*h = (HostAddress){
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.cond = COND_AL,
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.base = addrlo,
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.index = guest_base ? TCG_REG_GUEST_BASE : -1,
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.index_scratch = false,
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};
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#endif
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return ldst;
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}
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static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg datalo,
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static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg datalo,
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TCGReg datahi, HostAddress h)
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TCGReg datahi, HostAddress h)
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{
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{
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@ -1799,37 +1785,28 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi,
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MemOpIdx oi, TCGType data_type)
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MemOpIdx oi, TCGType data_type)
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{
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{
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MemOp opc = get_memop(oi);
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MemOp opc = get_memop(oi);
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TCGLabelQemuLdst *ldst;
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HostAddress h;
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HostAddress h;
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#ifdef CONFIG_SOFTMMU
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ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, true);
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h.cond = COND_AL;
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if (ldst) {
|
||||||
h.base = addrlo;
|
ldst->type = data_type;
|
||||||
h.index_scratch = true;
|
ldst->datalo_reg = datalo;
|
||||||
h.index = tcg_out_tlb_read(s, addrlo, addrhi, opc, get_mmuidx(oi), 1);
|
ldst->datahi_reg = datahi;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* This a conditional BL only to load a pointer within this opcode into
|
* This a conditional BL only to load a pointer within this
|
||||||
* LR for the slow path. We will not be using the value for a tail call.
|
* opcode into LR for the slow path. We will not be using
|
||||||
*/
|
* the value for a tail call.
|
||||||
tcg_insn_unit *label_ptr = s->code_ptr;
|
*/
|
||||||
tcg_out_bl_imm(s, COND_NE, 0);
|
ldst->label_ptr[0] = s->code_ptr;
|
||||||
|
tcg_out_bl_imm(s, COND_NE, 0);
|
||||||
|
|
||||||
tcg_out_qemu_ld_direct(s, opc, datalo, datahi, h);
|
tcg_out_qemu_ld_direct(s, opc, datalo, datahi, h);
|
||||||
|
ldst->raddr = tcg_splitwx_to_rx(s->code_ptr);
|
||||||
add_qemu_ldst_label(s, true, oi, data_type, datalo, datahi,
|
} else {
|
||||||
addrlo, addrhi, s->code_ptr, label_ptr);
|
tcg_out_qemu_ld_direct(s, opc, datalo, datahi, h);
|
||||||
#else
|
|
||||||
unsigned a_bits = get_alignment_bits(opc);
|
|
||||||
if (a_bits) {
|
|
||||||
tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
h.cond = COND_AL;
|
|
||||||
h.base = addrlo;
|
|
||||||
h.index = guest_base ? TCG_REG_GUEST_BASE : -1;
|
|
||||||
h.index_scratch = false;
|
|
||||||
tcg_out_qemu_ld_direct(s, opc, datalo, datahi, h);
|
|
||||||
#endif
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg datalo,
|
static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg datalo,
|
||||||
|
|
@ -1891,35 +1868,25 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi,
|
||||||
MemOpIdx oi, TCGType data_type)
|
MemOpIdx oi, TCGType data_type)
|
||||||
{
|
{
|
||||||
MemOp opc = get_memop(oi);
|
MemOp opc = get_memop(oi);
|
||||||
|
TCGLabelQemuLdst *ldst;
|
||||||
HostAddress h;
|
HostAddress h;
|
||||||
|
|
||||||
#ifdef CONFIG_SOFTMMU
|
ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, false);
|
||||||
h.cond = COND_EQ;
|
if (ldst) {
|
||||||
h.base = addrlo;
|
ldst->type = data_type;
|
||||||
h.index_scratch = true;
|
ldst->datalo_reg = datalo;
|
||||||
h.index = tcg_out_tlb_read(s, addrlo, addrhi, opc, get_mmuidx(oi), 0);
|
ldst->datahi_reg = datahi;
|
||||||
tcg_out_qemu_st_direct(s, opc, datalo, datahi, h);
|
|
||||||
|
|
||||||
/* The conditional call must come last, as we're going to return here. */
|
|
||||||
tcg_insn_unit *label_ptr = s->code_ptr;
|
|
||||||
tcg_out_bl_imm(s, COND_NE, 0);
|
|
||||||
|
|
||||||
add_qemu_ldst_label(s, false, oi, data_type, datalo, datahi,
|
|
||||||
addrlo, addrhi, s->code_ptr, label_ptr);
|
|
||||||
#else
|
|
||||||
unsigned a_bits = get_alignment_bits(opc);
|
|
||||||
|
|
||||||
h.cond = COND_AL;
|
|
||||||
if (a_bits) {
|
|
||||||
tcg_out_test_alignment(s, false, addrlo, addrhi, a_bits);
|
|
||||||
h.cond = COND_EQ;
|
h.cond = COND_EQ;
|
||||||
}
|
tcg_out_qemu_st_direct(s, opc, datalo, datahi, h);
|
||||||
|
|
||||||
h.base = addrlo;
|
/* The conditional call is last, as we're going to return here. */
|
||||||
h.index = guest_base ? TCG_REG_GUEST_BASE : -1;
|
ldst->label_ptr[0] = s->code_ptr;
|
||||||
h.index_scratch = false;
|
tcg_out_bl_imm(s, COND_NE, 0);
|
||||||
tcg_out_qemu_st_direct(s, opc, datalo, datahi, h);
|
ldst->raddr = tcg_splitwx_to_rx(s->code_ptr);
|
||||||
#endif
|
} else {
|
||||||
|
tcg_out_qemu_st_direct(s, opc, datalo, datahi, h);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
static void tcg_out_epilogue(TCGContext *s);
|
static void tcg_out_epilogue(TCGContext *s);
|
||||||
|
|
|
||||||
Loading…
Add table
Add a link
Reference in a new issue