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target-i386: Implement ANDN

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As this is the first of the BMI insns to be implemented,
this carries quite a bit more baggage than normal.

Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson 2013-01-23 16:17:10 -08:00
parent 111994ee05
commit 7073fbada7
2 changed files with 22 additions and 7 deletions
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19
target-i386/translate.c
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@ -2955,8 +2955,9 @@ static const SSEFunc_0_epp sse_op_table1[256][4] = {
[0xc6] = { (SSEFunc_0_epp)gen_helper_shufps,
(SSEFunc_0_epp)gen_helper_shufpd }, /* XXX: casts */
[0x38] = { SSE_SPECIAL, SSE_SPECIAL, NULL, SSE_SPECIAL }, /* SSSE3/SSE4 */
[0x3a] = { SSE_SPECIAL, SSE_SPECIAL }, /* SSSE3/SSE4 */
/* SSSE3, SSE4, MOVBE, CRC32, BMI1, BMI2, ADX. */
[0x38] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL },
[0x3a] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL },
/* MMX ops and their SSE extensions */
[0x60] = MMX_OP2(punpcklbw),
@ -4011,6 +4012,20 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
}
break;
case 0x0f2: /* andn Gy, By, Ey */
if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI1)
|| !(s->prefix & PREFIX_VEX)
|| s->vex_l != 0) {
goto illegal_op;
}
ot = s->dflag == 2 ? OT_QUAD : OT_LONG;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
tcg_gen_andc_tl(cpu_T[0], cpu_regs[s->vex_v], cpu_T[0]);
gen_op_mov_reg_T0(ot, reg);
gen_op_update1_cc();
set_cc_op(s, CC_OP_LOGICB + ot);
break;
default:
goto illegal_op;
}