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tcg/ppc: Introduce prepare_host_addr
Merge tcg_out_tlb_load, add_qemu_ldst_label, tcg_out_test_alignment, and some code that lived in both tcg_out_qemu_ld and tcg_out_qemu_st into one function that returns HostAddress and TCGLabelQemuLdst structures. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
5b7208daa0
commit
7069e03699
1 changed files with 172 additions and 209 deletions
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@ -2003,140 +2003,6 @@ static void * const qemu_st_helpers[(MO_SIZE | MO_BSWAP) + 1] = {
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[MO_BEUQ] = helper_be_stq_mmu,
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[MO_BEUQ] = helper_be_stq_mmu,
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};
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};
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/* We expect to use a 16-bit negative offset from ENV. */
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QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
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QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768);
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/* Perform the TLB load and compare. Places the result of the comparison
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in CR7, loads the addend of the TLB into R3, and returns the register
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containing the guest address (zero-extended into R4). Clobbers R0 and R2. */
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static TCGReg tcg_out_tlb_read(TCGContext *s, MemOp opc,
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TCGReg addrlo, TCGReg addrhi,
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int mem_index, bool is_read)
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{
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int cmp_off
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= (is_read
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? offsetof(CPUTLBEntry, addr_read)
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: offsetof(CPUTLBEntry, addr_write));
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int fast_off = TLB_MASK_TABLE_OFS(mem_index);
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int mask_off = fast_off + offsetof(CPUTLBDescFast, mask);
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int table_off = fast_off + offsetof(CPUTLBDescFast, table);
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unsigned s_bits = opc & MO_SIZE;
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unsigned a_bits = get_alignment_bits(opc);
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/* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
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tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_AREG0, mask_off);
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tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R4, TCG_AREG0, table_off);
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/* Extract the page index, shifted into place for tlb index. */
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if (TCG_TARGET_REG_BITS == 32) {
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tcg_out_shri32(s, TCG_REG_TMP1, addrlo,
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TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
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} else {
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tcg_out_shri64(s, TCG_REG_TMP1, addrlo,
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TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
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}
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tcg_out32(s, AND | SAB(TCG_REG_R3, TCG_REG_R3, TCG_REG_TMP1));
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/* Load the TLB comparator. */
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if (cmp_off == 0 && TCG_TARGET_REG_BITS >= TARGET_LONG_BITS) {
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uint32_t lxu = (TCG_TARGET_REG_BITS == 32 || TARGET_LONG_BITS == 32
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? LWZUX : LDUX);
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tcg_out32(s, lxu | TAB(TCG_REG_TMP1, TCG_REG_R3, TCG_REG_R4));
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} else {
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tcg_out32(s, ADD | TAB(TCG_REG_R3, TCG_REG_R3, TCG_REG_R4));
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if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
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tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP1, TCG_REG_R3, cmp_off + 4);
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tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R4, TCG_REG_R3, cmp_off);
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} else {
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tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP1, TCG_REG_R3, cmp_off);
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}
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}
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/* Load the TLB addend for use on the fast path. Do this asap
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to minimize any load use delay. */
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tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_REG_R3,
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offsetof(CPUTLBEntry, addend));
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/* Clear the non-page, non-alignment bits from the address */
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if (TCG_TARGET_REG_BITS == 32) {
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/* We don't support unaligned accesses on 32-bits.
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* Preserve the bottom bits and thus trigger a comparison
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* failure on unaligned accesses.
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*/
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if (a_bits < s_bits) {
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a_bits = s_bits;
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}
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tcg_out_rlw(s, RLWINM, TCG_REG_R0, addrlo, 0,
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(32 - a_bits) & 31, 31 - TARGET_PAGE_BITS);
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} else {
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TCGReg t = addrlo;
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/* If the access is unaligned, we need to make sure we fail if we
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* cross a page boundary. The trick is to add the access size-1
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* to the address before masking the low bits. That will make the
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* address overflow to the next page if we cross a page boundary,
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* which will then force a mismatch of the TLB compare.
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*/
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if (a_bits < s_bits) {
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unsigned a_mask = (1 << a_bits) - 1;
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unsigned s_mask = (1 << s_bits) - 1;
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tcg_out32(s, ADDI | TAI(TCG_REG_R0, t, s_mask - a_mask));
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t = TCG_REG_R0;
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}
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/* Mask the address for the requested alignment. */
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if (TARGET_LONG_BITS == 32) {
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tcg_out_rlw(s, RLWINM, TCG_REG_R0, t, 0,
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(32 - a_bits) & 31, 31 - TARGET_PAGE_BITS);
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/* Zero-extend the address for use in the final address. */
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tcg_out_ext32u(s, TCG_REG_R4, addrlo);
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addrlo = TCG_REG_R4;
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} else if (a_bits == 0) {
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tcg_out_rld(s, RLDICR, TCG_REG_R0, t, 0, 63 - TARGET_PAGE_BITS);
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} else {
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tcg_out_rld(s, RLDICL, TCG_REG_R0, t,
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64 - TARGET_PAGE_BITS, TARGET_PAGE_BITS - a_bits);
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tcg_out_rld(s, RLDICL, TCG_REG_R0, TCG_REG_R0, TARGET_PAGE_BITS, 0);
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}
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}
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if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
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tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1,
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0, 7, TCG_TYPE_I32);
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tcg_out_cmp(s, TCG_COND_EQ, addrhi, TCG_REG_R4, 0, 6, TCG_TYPE_I32);
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tcg_out32(s, CRAND | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ));
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} else {
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tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1,
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0, 7, TCG_TYPE_TL);
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}
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return addrlo;
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}
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/* Record the context of a call to the out of line helper code for the slow
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path for a load or store, so that we can later generate the correct
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helper code. */
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static void add_qemu_ldst_label(TCGContext *s, bool is_ld,
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TCGType type, MemOpIdx oi,
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TCGReg datalo_reg, TCGReg datahi_reg,
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TCGReg addrlo_reg, TCGReg addrhi_reg,
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tcg_insn_unit *raddr, tcg_insn_unit *lptr)
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{
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TCGLabelQemuLdst *label = new_ldst_label(s);
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label->is_ld = is_ld;
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label->type = type;
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label->oi = oi;
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label->datalo_reg = datalo_reg;
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label->datahi_reg = datahi_reg;
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label->addrlo_reg = addrlo_reg;
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label->addrhi_reg = addrhi_reg;
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label->raddr = tcg_splitwx_to_rx(raddr);
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label->label_ptr[0] = lptr;
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}
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static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
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static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
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{
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{
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MemOpIdx oi = lb->oi;
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MemOpIdx oi = lb->oi;
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@ -2225,27 +2091,6 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
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return true;
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return true;
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}
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}
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#else
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#else
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static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addrlo,
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TCGReg addrhi, unsigned a_bits)
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{
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unsigned a_mask = (1 << a_bits) - 1;
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TCGLabelQemuLdst *label = new_ldst_label(s);
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label->is_ld = is_ld;
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label->addrlo_reg = addrlo;
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label->addrhi_reg = addrhi;
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/* We are expecting a_bits to max out at 7, much lower than ANDI. */
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tcg_debug_assert(a_bits < 16);
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tcg_out32(s, ANDI | SAI(addrlo, TCG_REG_R0, a_mask));
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label->label_ptr[0] = s->code_ptr;
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tcg_out32(s, BC | BI(0, CR_EQ) | BO_COND_FALSE | LK);
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label->raddr = tcg_splitwx_to_rx(s->code_ptr);
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}
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static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l)
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static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l)
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{
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{
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if (!reloc_pc14(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) {
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if (!reloc_pc14(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) {
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@ -2294,37 +2139,171 @@ typedef struct {
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TCGReg index;
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TCGReg index;
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} HostAddress;
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} HostAddress;
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/*
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* For softmmu, perform the TLB load and compare.
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* For useronly, perform any required alignment tests.
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* In both cases, return a TCGLabelQemuLdst structure if the slow path
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* is required and fill in @h with the host address for the fast path.
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*/
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static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
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TCGReg addrlo, TCGReg addrhi,
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MemOpIdx oi, bool is_ld)
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{
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TCGLabelQemuLdst *ldst = NULL;
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MemOp opc = get_memop(oi);
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unsigned a_bits = get_alignment_bits(opc);
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#ifdef CONFIG_SOFTMMU
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int mem_index = get_mmuidx(oi);
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int cmp_off = is_ld ? offsetof(CPUTLBEntry, addr_read)
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: offsetof(CPUTLBEntry, addr_write);
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int fast_off = TLB_MASK_TABLE_OFS(mem_index);
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int mask_off = fast_off + offsetof(CPUTLBDescFast, mask);
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int table_off = fast_off + offsetof(CPUTLBDescFast, table);
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unsigned s_bits = opc & MO_SIZE;
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ldst = new_ldst_label(s);
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ldst->is_ld = is_ld;
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ldst->oi = oi;
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ldst->addrlo_reg = addrlo;
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ldst->addrhi_reg = addrhi;
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/* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
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QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
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QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768);
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tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_AREG0, mask_off);
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tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R4, TCG_AREG0, table_off);
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/* Extract the page index, shifted into place for tlb index. */
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if (TCG_TARGET_REG_BITS == 32) {
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tcg_out_shri32(s, TCG_REG_TMP1, addrlo,
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TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
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} else {
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tcg_out_shri64(s, TCG_REG_TMP1, addrlo,
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TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
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}
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tcg_out32(s, AND | SAB(TCG_REG_R3, TCG_REG_R3, TCG_REG_TMP1));
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/* Load the TLB comparator. */
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if (cmp_off == 0 && TCG_TARGET_REG_BITS >= TARGET_LONG_BITS) {
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uint32_t lxu = (TCG_TARGET_REG_BITS == 32 || TARGET_LONG_BITS == 32
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? LWZUX : LDUX);
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tcg_out32(s, lxu | TAB(TCG_REG_TMP1, TCG_REG_R3, TCG_REG_R4));
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} else {
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tcg_out32(s, ADD | TAB(TCG_REG_R3, TCG_REG_R3, TCG_REG_R4));
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if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
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tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP1, TCG_REG_R3, cmp_off + 4);
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tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R4, TCG_REG_R3, cmp_off);
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} else {
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tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP1, TCG_REG_R3, cmp_off);
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}
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}
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/*
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* Load the TLB addend for use on the fast path.
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* Do this asap to minimize any load use delay.
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*/
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h->base = TCG_REG_R3;
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tcg_out_ld(s, TCG_TYPE_PTR, h->base, TCG_REG_R3,
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offsetof(CPUTLBEntry, addend));
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/* Clear the non-page, non-alignment bits from the address */
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if (TCG_TARGET_REG_BITS == 32) {
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/*
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* We don't support unaligned accesses on 32-bits.
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* Preserve the bottom bits and thus trigger a comparison
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* failure on unaligned accesses.
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*/
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if (a_bits < s_bits) {
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a_bits = s_bits;
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}
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tcg_out_rlw(s, RLWINM, TCG_REG_R0, addrlo, 0,
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(32 - a_bits) & 31, 31 - TARGET_PAGE_BITS);
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} else {
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TCGReg t = addrlo;
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/*
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* If the access is unaligned, we need to make sure we fail if we
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* cross a page boundary. The trick is to add the access size-1
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* to the address before masking the low bits. That will make the
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* address overflow to the next page if we cross a page boundary,
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* which will then force a mismatch of the TLB compare.
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*/
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if (a_bits < s_bits) {
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unsigned a_mask = (1 << a_bits) - 1;
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unsigned s_mask = (1 << s_bits) - 1;
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tcg_out32(s, ADDI | TAI(TCG_REG_R0, t, s_mask - a_mask));
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t = TCG_REG_R0;
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}
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/* Mask the address for the requested alignment. */
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if (TARGET_LONG_BITS == 32) {
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tcg_out_rlw(s, RLWINM, TCG_REG_R0, t, 0,
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(32 - a_bits) & 31, 31 - TARGET_PAGE_BITS);
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/* Zero-extend the address for use in the final address. */
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tcg_out_ext32u(s, TCG_REG_R4, addrlo);
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addrlo = TCG_REG_R4;
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} else if (a_bits == 0) {
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tcg_out_rld(s, RLDICR, TCG_REG_R0, t, 0, 63 - TARGET_PAGE_BITS);
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} else {
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tcg_out_rld(s, RLDICL, TCG_REG_R0, t,
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64 - TARGET_PAGE_BITS, TARGET_PAGE_BITS - a_bits);
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tcg_out_rld(s, RLDICL, TCG_REG_R0, TCG_REG_R0, TARGET_PAGE_BITS, 0);
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}
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}
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h->index = addrlo;
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if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
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tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1,
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0, 7, TCG_TYPE_I32);
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tcg_out_cmp(s, TCG_COND_EQ, addrhi, TCG_REG_R4, 0, 6, TCG_TYPE_I32);
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tcg_out32(s, CRAND | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ));
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} else {
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||||||
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tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1,
|
||||||
|
0, 7, TCG_TYPE_TL);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Load a pointer into the current opcode w/conditional branch-link. */
|
||||||
|
ldst->label_ptr[0] = s->code_ptr;
|
||||||
|
tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK);
|
||||||
|
#else
|
||||||
|
if (a_bits) {
|
||||||
|
ldst = new_ldst_label(s);
|
||||||
|
ldst->is_ld = is_ld;
|
||||||
|
ldst->oi = oi;
|
||||||
|
ldst->addrlo_reg = addrlo;
|
||||||
|
ldst->addrhi_reg = addrhi;
|
||||||
|
|
||||||
|
/* We are expecting a_bits to max out at 7, much lower than ANDI. */
|
||||||
|
tcg_debug_assert(a_bits < 16);
|
||||||
|
tcg_out32(s, ANDI | SAI(addrlo, TCG_REG_R0, (1 << a_bits) - 1));
|
||||||
|
|
||||||
|
ldst->label_ptr[0] = s->code_ptr;
|
||||||
|
tcg_out32(s, BC | BI(0, CR_EQ) | BO_COND_FALSE | LK);
|
||||||
|
}
|
||||||
|
|
||||||
|
h->base = guest_base ? TCG_GUEST_BASE_REG : 0;
|
||||||
|
h->index = addrlo;
|
||||||
|
if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
|
||||||
|
tcg_out_ext32u(s, TCG_REG_TMP1, addrlo);
|
||||||
|
h->index = TCG_REG_TMP1;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
return ldst;
|
||||||
|
}
|
||||||
|
|
||||||
static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi,
|
static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi,
|
||||||
TCGReg addrlo, TCGReg addrhi,
|
TCGReg addrlo, TCGReg addrhi,
|
||||||
MemOpIdx oi, TCGType data_type)
|
MemOpIdx oi, TCGType data_type)
|
||||||
{
|
{
|
||||||
MemOp opc = get_memop(oi);
|
MemOp opc = get_memop(oi);
|
||||||
MemOp s_bits = opc & MO_SIZE;
|
TCGLabelQemuLdst *ldst;
|
||||||
HostAddress h;
|
HostAddress h;
|
||||||
|
|
||||||
#ifdef CONFIG_SOFTMMU
|
ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, true);
|
||||||
tcg_insn_unit *label_ptr;
|
|
||||||
|
|
||||||
h.index = tcg_out_tlb_read(s, opc, addrlo, addrhi, get_mmuidx(oi), true);
|
if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) {
|
||||||
h.base = TCG_REG_R3;
|
|
||||||
|
|
||||||
/* Load a pointer into the current opcode w/conditional branch-link. */
|
|
||||||
label_ptr = s->code_ptr;
|
|
||||||
tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK);
|
|
||||||
#else /* !CONFIG_SOFTMMU */
|
|
||||||
unsigned a_bits = get_alignment_bits(opc);
|
|
||||||
if (a_bits) {
|
|
||||||
tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits);
|
|
||||||
}
|
|
||||||
h.base = guest_base ? TCG_GUEST_BASE_REG : 0;
|
|
||||||
h.index = addrlo;
|
|
||||||
if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
|
|
||||||
tcg_out_ext32u(s, TCG_REG_TMP1, addrlo);
|
|
||||||
h.index = TCG_REG_TMP1;
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) {
|
|
||||||
if (opc & MO_BSWAP) {
|
if (opc & MO_BSWAP) {
|
||||||
tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4));
|
tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4));
|
||||||
tcg_out32(s, LWBRX | TAB(datalo, h.base, h.index));
|
tcg_out32(s, LWBRX | TAB(datalo, h.base, h.index));
|
||||||
|
|
@ -2357,10 +2336,12 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi,
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
#ifdef CONFIG_SOFTMMU
|
if (ldst) {
|
||||||
add_qemu_ldst_label(s, true, data_type, oi, datalo, datahi,
|
ldst->type = data_type;
|
||||||
addrlo, addrhi, s->code_ptr, label_ptr);
|
ldst->datalo_reg = datalo;
|
||||||
#endif
|
ldst->datahi_reg = datahi;
|
||||||
|
ldst->raddr = tcg_splitwx_to_rx(s->code_ptr);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi,
|
static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi,
|
||||||
|
|
@ -2368,32 +2349,12 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi,
|
||||||
MemOpIdx oi, TCGType data_type)
|
MemOpIdx oi, TCGType data_type)
|
||||||
{
|
{
|
||||||
MemOp opc = get_memop(oi);
|
MemOp opc = get_memop(oi);
|
||||||
MemOp s_bits = opc & MO_SIZE;
|
TCGLabelQemuLdst *ldst;
|
||||||
HostAddress h;
|
HostAddress h;
|
||||||
|
|
||||||
#ifdef CONFIG_SOFTMMU
|
ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, false);
|
||||||
tcg_insn_unit *label_ptr;
|
|
||||||
|
|
||||||
h.index = tcg_out_tlb_read(s, opc, addrlo, addrhi, get_mmuidx(oi), false);
|
if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) {
|
||||||
h.base = TCG_REG_R3;
|
|
||||||
|
|
||||||
/* Load a pointer into the current opcode w/conditional branch-link. */
|
|
||||||
label_ptr = s->code_ptr;
|
|
||||||
tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK);
|
|
||||||
#else /* !CONFIG_SOFTMMU */
|
|
||||||
unsigned a_bits = get_alignment_bits(opc);
|
|
||||||
if (a_bits) {
|
|
||||||
tcg_out_test_alignment(s, false, addrlo, addrhi, a_bits);
|
|
||||||
}
|
|
||||||
h.base = guest_base ? TCG_GUEST_BASE_REG : 0;
|
|
||||||
h.index = addrlo;
|
|
||||||
if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
|
|
||||||
tcg_out_ext32u(s, TCG_REG_TMP1, addrlo);
|
|
||||||
h.index = TCG_REG_TMP1;
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) {
|
|
||||||
if (opc & MO_BSWAP) {
|
if (opc & MO_BSWAP) {
|
||||||
tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4));
|
tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4));
|
||||||
tcg_out32(s, STWBRX | SAB(datalo, h.base, h.index));
|
tcg_out32(s, STWBRX | SAB(datalo, h.base, h.index));
|
||||||
|
|
@ -2418,10 +2379,12 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi,
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
#ifdef CONFIG_SOFTMMU
|
if (ldst) {
|
||||||
add_qemu_ldst_label(s, false, data_type, oi, datalo, datahi,
|
ldst->type = data_type;
|
||||||
addrlo, addrhi, s->code_ptr, label_ptr);
|
ldst->datalo_reg = datalo;
|
||||||
#endif
|
ldst->datahi_reg = datahi;
|
||||||
|
ldst->raddr = tcg_splitwx_to_rx(s->code_ptr);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
|
static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
|
||||||
|
|
|
||||||
Loading…
Add table
Add a link
Reference in a new issue