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exec: Declare tlb_flush*() in 'exec/cputlb.h'
Move CPU TLB related methods to "exec/cputlb.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-ID: <20241114011310.3615-19-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé
Richard Henderson
parent
bcde46f57d
commit
6ff5da1600
34 changed files with 224 additions and 211 deletions
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@ -25,21 +25,14 @@
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#include "exec/memattrs.h"
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#include "exec/vaddr.h"
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#ifdef CONFIG_TCG
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#if !defined(CONFIG_USER_ONLY)
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/* cputlb.c */
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#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
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void tlb_protect_code(ram_addr_t ram_addr);
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void tlb_unprotect_code(ram_addr_t ram_addr);
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#endif
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#endif /* CONFIG_TCG */
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#ifndef CONFIG_USER_ONLY
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void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length);
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void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length);
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#endif
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/**
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@ -101,4 +94,193 @@ void tlb_set_page(CPUState *cpu, vaddr addr,
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hwaddr paddr, int prot,
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int mmu_idx, vaddr size);
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#endif
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#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
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/**
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* tlb_flush_page:
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* @cpu: CPU whose TLB should be flushed
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* @addr: virtual address of page to be flushed
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*
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* Flush one page from the TLB of the specified CPU, for all
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* MMU indexes.
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*/
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void tlb_flush_page(CPUState *cpu, vaddr addr);
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/**
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* tlb_flush_page_all_cpus_synced:
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* @cpu: src CPU of the flush
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* @addr: virtual address of page to be flushed
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*
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* Flush one page from the TLB of all CPUs, for all
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* MMU indexes.
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*
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* When this function returns, no CPUs will subsequently perform
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* translations using the flushed TLBs.
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*/
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void tlb_flush_page_all_cpus_synced(CPUState *src, vaddr addr);
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/**
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* tlb_flush:
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* @cpu: CPU whose TLB should be flushed
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*
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* Flush the entire TLB for the specified CPU. Most CPU architectures
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* allow the implementation to drop entries from the TLB at any time
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* so this is generally safe. If more selective flushing is required
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* use one of the other functions for efficiency.
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*/
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void tlb_flush(CPUState *cpu);
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/**
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* tlb_flush_all_cpus_synced:
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* @cpu: src CPU of the flush
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*
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* Flush the entire TLB for all CPUs, for all MMU indexes.
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*
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* When this function returns, no CPUs will subsequently perform
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* translations using the flushed TLBs.
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*/
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void tlb_flush_all_cpus_synced(CPUState *src_cpu);
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/**
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* tlb_flush_page_by_mmuidx:
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* @cpu: CPU whose TLB should be flushed
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* @addr: virtual address of page to be flushed
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* @idxmap: bitmap of MMU indexes to flush
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*
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* Flush one page from the TLB of the specified CPU, for the specified
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* MMU indexes.
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*/
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void tlb_flush_page_by_mmuidx(CPUState *cpu, vaddr addr,
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uint16_t idxmap);
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/**
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* tlb_flush_page_by_mmuidx_all_cpus_synced:
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* @cpu: Originating CPU of the flush
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* @addr: virtual address of page to be flushed
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* @idxmap: bitmap of MMU indexes to flush
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*
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* Flush one page from the TLB of all CPUs, for the specified
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* MMU indexes.
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*
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* When this function returns, no CPUs will subsequently perform
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* translations using the flushed TLBs.
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*/
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void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr,
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uint16_t idxmap);
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/**
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* tlb_flush_by_mmuidx:
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* @cpu: CPU whose TLB should be flushed
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* @wait: If true ensure synchronisation by exiting the cpu_loop
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* @idxmap: bitmap of MMU indexes to flush
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*
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* Flush all entries from the TLB of the specified CPU, for the specified
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* MMU indexes.
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*/
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void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap);
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/**
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* tlb_flush_by_mmuidx_all_cpus_synced:
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* @cpu: Originating CPU of the flush
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* @idxmap: bitmap of MMU indexes to flush
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*
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* Flush all entries from the TLB of all CPUs, for the specified
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* MMU indexes.
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*
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* When this function returns, no CPUs will subsequently perform
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* translations using the flushed TLBs.
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*/
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void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, uint16_t idxmap);
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/**
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* tlb_flush_page_bits_by_mmuidx
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* @cpu: CPU whose TLB should be flushed
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* @addr: virtual address of page to be flushed
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* @idxmap: bitmap of mmu indexes to flush
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* @bits: number of significant bits in address
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*
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* Similar to tlb_flush_page_mask, but with a bitmap of indexes.
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*/
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void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, vaddr addr,
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uint16_t idxmap, unsigned bits);
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/* Similarly, with broadcast and syncing. */
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void tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr,
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uint16_t idxmap,
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unsigned bits);
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/**
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* tlb_flush_range_by_mmuidx
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* @cpu: CPU whose TLB should be flushed
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* @addr: virtual address of the start of the range to be flushed
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* @len: length of range to be flushed
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* @idxmap: bitmap of mmu indexes to flush
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* @bits: number of significant bits in address
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*
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* For each mmuidx in @idxmap, flush all pages within [@addr,@addr+@len),
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* comparing only the low @bits worth of each virtual page.
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*/
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void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr,
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vaddr len, uint16_t idxmap,
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unsigned bits);
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/* Similarly, with broadcast and syncing. */
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void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu,
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vaddr addr,
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vaddr len,
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uint16_t idxmap,
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unsigned bits);
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#else
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static inline void tlb_flush_page(CPUState *cpu, vaddr addr)
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{
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}
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static inline void tlb_flush_page_all_cpus_synced(CPUState *src, vaddr addr)
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{
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}
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static inline void tlb_flush(CPUState *cpu)
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{
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}
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static inline void tlb_flush_all_cpus_synced(CPUState *src_cpu)
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{
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}
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static inline void tlb_flush_page_by_mmuidx(CPUState *cpu,
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vaddr addr, uint16_t idxmap)
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{
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}
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static inline void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap)
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{
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}
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static inline void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu,
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vaddr addr,
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uint16_t idxmap)
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{
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}
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static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu,
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uint16_t idxmap)
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{
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}
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static inline void tlb_flush_page_bits_by_mmuidx(CPUState *cpu,
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vaddr addr,
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uint16_t idxmap,
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unsigned bits)
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{
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}
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static inline void
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tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr,
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uint16_t idxmap, unsigned bits)
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{
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}
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static inline void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr,
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vaddr len, uint16_t idxmap,
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unsigned bits)
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{
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}
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static inline void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu,
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vaddr addr,
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vaddr len,
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uint16_t idxmap,
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unsigned bits)
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{
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}
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#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
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#endif /* CPUTLB_H */
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