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target/arm/cpu64: max cpu: Support sve properties with KVM

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Extend the SVE vq map initialization and validation with KVM's
supported vector lengths when KVM is enabled. In order to determine
and select supported lengths we add two new KVM functions for getting
and setting the KVM_REG_ARM64_SVE_VLS pseudo-register.

This patch has been co-authored with Richard Henderson, who reworked
the target/arm/cpu64.c changes in order to push all the validation and
auto-enabling/disabling steps into the finalizer, resulting in a nice
LOC reduction.

Signed-off-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>
Message-id: 20191031142734.8590-9-drjones@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Andrew Jones 2019-10-31 15:27:33 +01:00 • committed by Peter Maydell
parent 0cdb4020b3
commit 6fa8a37949
5 changed files with 379 additions and 58 deletions
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45
docs/arm-cpu-features.rst
View file

@ -191,10 +191,18 @@ SVE CPU Property Dependencies and Constraints
1) At least one vector length must be enabled when `sve` is enabled.
2) If a vector length `N` is enabled, then all power-of-two vector
lengths smaller than `N` must also be enabled. E.g. if `sve512`
is enabled, then the 128-bit and 256-bit vector lengths must also
be enabled.
2) If a vector length `N` is enabled, then, when KVM is enabled, all
smaller, host supported vector lengths must also be enabled. If
KVM is not enabled, then only all the smaller, power-of-two vector
lengths must be enabled. E.g. with KVM if the host supports all
vector lengths up to 512-bits (128, 256, 384, 512), then if `sve512`
is enabled, the 128-bit vector length, 256-bit vector length, and
384-bit vector length must also be enabled. Without KVM, the 384-bit
vector length would not be required.
3) If KVM is enabled then only vector lengths that the host CPU type
support may be enabled. If SVE is not supported by the host, then
no `sve*` properties may be enabled.
SVE CPU Property Parsing Semantics
----------------------------------
@ -209,8 +217,10 @@ SVE CPU Property Parsing Semantics
an error is generated.
2) If SVE is enabled (`sve=on`), but no `sve<N>` CPU properties are
provided, then all supported vector lengths are enabled, including
the non-power-of-two lengths.
provided, then all supported vector lengths are enabled, which when
KVM is not in use means including the non-power-of-two lengths, and,
when KVM is in use, it means all vector lengths supported by the host
processor.
3) If SVE is enabled, then an error is generated when attempting to
disable the last enabled vector length (see constraint (1) of "SVE
@ -221,20 +231,31 @@ SVE CPU Property Parsing Semantics
has been explicitly disabled, then an error is generated (see
constraint (2) of "SVE CPU Property Dependencies and Constraints").
5) If one or more `sve<N>` CPU properties are set `off`, but no `sve<N>`,
5) When KVM is enabled, if the host does not support SVE, then an error
is generated when attempting to enable any `sve*` properties (see
constraint (3) of "SVE CPU Property Dependencies and Constraints").
6) When KVM is enabled, if the host does support SVE, then an error is
generated when attempting to enable any vector lengths not supported
by the host (see constraint (3) of "SVE CPU Property Dependencies and
Constraints").
7) If one or more `sve<N>` CPU properties are set `off`, but no `sve<N>`,
CPU properties are set `on`, then the specified vector lengths are
disabled but the default for any unspecified lengths remains enabled.
Disabling a power-of-two vector length also disables all vector
lengths larger than the power-of-two length (see constraint (2) of
"SVE CPU Property Dependencies and Constraints").
When KVM is not enabled, disabling a power-of-two vector length also
disables all vector lengths larger than the power-of-two length.
When KVM is enabled, then disabling any supported vector length also
disables all larger vector lengths (see constraint (2) of "SVE CPU
Property Dependencies and Constraints").
6) If one or more `sve<N>` CPU properties are set to `on`, then they
8) If one or more `sve<N>` CPU properties are set to `on`, then they
are enabled and all unspecified lengths default to disabled, except
for the required lengths per constraint (2) of "SVE CPU Property
Dependencies and Constraints", which will even be auto-enabled if
they were not explicitly enabled.
7) If SVE was disabled (`sve=off`), allowing all vector lengths to be
9) If SVE was disabled (`sve=off`), allowing all vector lengths to be
explicitly disabled (i.e. avoiding the error specified in (3) of
"SVE CPU Property Parsing Semantics"), then if later an `sve=on` is
provided an error will be generated. To avoid this error, one must