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target/microblaze: Fix width of ESR

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The exception status register is only 32-bits wide.
Do not use a 64-bit type to represent it.

Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2020-08-19 22:37:40 -07:00
parent 3e0e16ae1e
commit 6efd55995a
5 changed files with 12 additions and 12 deletions
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2
target/microblaze/op_helper.c
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@ -76,7 +76,7 @@ void helper_debug(CPUMBState *env)
int i;
qemu_log("PC=%08x\n", env->pc);
qemu_log("rmsr=%x resr=%" PRIx64 " rear=%" PRIx64 " "
qemu_log("rmsr=%x resr=%x rear=%" PRIx64 " "
"debug[%x] imm=%x iflags=%x\n",
env->msr, env->esr, env->ear,
env->debug, env->imm, env->iflags);