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target/riscv: rvb: pack two words into one register

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Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210505160620.15723-6-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Kito Cheng 2021-05-06 00:06:06 +08:00 • committed by Alistair Francis
parent 0bcdb686e5
commit 6ef5843182
3 changed files with 78 additions and 0 deletions
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32
target/riscv/insn_trans/trans_rvb.c.inc
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@ -53,6 +53,24 @@ static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
return gen_arith(ctx, a, tcg_gen_eqv_tl);
}
static bool trans_pack(DisasContext *ctx, arg_pack *a)
{
REQUIRE_EXT(ctx, RVB);
return gen_arith(ctx, a, gen_pack);
}
static bool trans_packu(DisasContext *ctx, arg_packu *a)
{
REQUIRE_EXT(ctx, RVB);
return gen_arith(ctx, a, gen_packu);
}
static bool trans_packh(DisasContext *ctx, arg_packh *a)
{
REQUIRE_EXT(ctx, RVB);
return gen_arith(ctx, a, gen_packh);
}
static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
{
REQUIRE_64BIT(ctx);
@ -73,3 +91,17 @@ static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
REQUIRE_EXT(ctx, RVB);
return gen_unary(ctx, a, gen_cpopw);
}
static bool trans_packw(DisasContext *ctx, arg_packw *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVB);
return gen_arith(ctx, a, gen_packw);
}
static bool trans_packuw(DisasContext *ctx, arg_packuw *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVB);
return gen_arith(ctx, a, gen_packuw);
}