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target: Unify QOM style

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Enforce the style described by commit 067109a11c ("docs/devel:
mention the spacing requirement for QOM"):

  The first declaration of a storage or class structure should
  always be the parent and leave a visual space between that
  declaration and the new code. It is also useful to separate
  backing for properties (options driven by the user) and internal
  state to make navigation easier.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20231013140116.255-2-philmd@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé 2023-10-13 11:21:51 +02:00
parent bb6cf6f016
commit 6ee45fac56
37 changed files with 4 additions and 84 deletions
Download patch file Download diff file Expand all files Collapse all files

2
target/alpha/cpu-qom.h
View file

@ -35,9 +35,7 @@ OBJECT_DECLARE_CPU_TYPE(AlphaCPU, AlphaCPUClass, ALPHA_CPU)
* An Alpha CPU model. * An Alpha CPU model.
*/ */
struct AlphaCPUClass { struct AlphaCPUClass {
/*< private >*/
CPUClass parent_class; CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize; DeviceRealize parent_realize;
DeviceReset parent_reset; DeviceReset parent_reset;

2
target/alpha/cpu.h
View file

@ -259,9 +259,7 @@ typedef struct CPUArchState {
* An Alpha CPU. * An Alpha CPU.
*/ */
struct ArchCPU { struct ArchCPU {
/*< private >*/
CPUState parent_obj; CPUState parent_obj;
/*< public >*/
CPUAlphaState env; CPUAlphaState env;

4
target/arm/cpu-qom.h
View file

@ -46,9 +46,7 @@ void aarch64_cpu_register(const ARMCPUInfo *info);
* An ARM CPU model. * An ARM CPU model.
*/ */
struct ARMCPUClass { struct ARMCPUClass {
/*< private >*/
CPUClass parent_class; CPUClass parent_class;
/*< public >*/
const ARMCPUInfo *info; const ARMCPUInfo *info;
DeviceRealize parent_realize; DeviceRealize parent_realize;
@ -62,9 +60,7 @@ DECLARE_CLASS_CHECKERS(AArch64CPUClass, AARCH64_CPU,
TYPE_AARCH64_CPU) TYPE_AARCH64_CPU)
struct AArch64CPUClass { struct AArch64CPUClass {
/*< private >*/
ARMCPUClass parent_class; ARMCPUClass parent_class;
/*< public >*/
}; };
void register_cp_regs_for_features(ARMCPU *cpu); void register_cp_regs_for_features(ARMCPU *cpu);

2
target/arm/cpu.h
View file

@ -852,9 +852,7 @@ typedef struct {
* An ARM CPU core. * An ARM CPU core.
*/ */
struct ArchCPU { struct ArchCPU {
/*< private >*/
CPUState parent_obj; CPUState parent_obj;
/*< public >*/
CPUARMState env; CPUARMState env;

3
target/avr/cpu-qom.h
View file

@ -36,9 +36,8 @@ OBJECT_DECLARE_CPU_TYPE(AVRCPU, AVRCPUClass, AVR_CPU)
* A AVR CPU model. * A AVR CPU model.
*/ */
struct AVRCPUClass { struct AVRCPUClass {
/*< private >*/
CPUClass parent_class; CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize; DeviceRealize parent_realize;
ResettablePhases parent_phases; ResettablePhases parent_phases;
}; };

2
target/avr/cpu.h
View file

@ -144,9 +144,7 @@ typedef struct CPUArchState {
* A AVR CPU. * A AVR CPU.
*/ */
struct ArchCPU { struct ArchCPU {
/*< private >*/
CPUState parent_obj; CPUState parent_obj;
/*< public >*/
CPUAVRState env; CPUAVRState env;
}; };

2
target/cris/cpu-qom.h
View file

@ -36,9 +36,7 @@ OBJECT_DECLARE_CPU_TYPE(CRISCPU, CRISCPUClass, CRIS_CPU)
* A CRIS CPU model. * A CRIS CPU model.
*/ */
struct CRISCPUClass { struct CRISCPUClass {
/*< private >*/
CPUClass parent_class; CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize; DeviceRealize parent_realize;
ResettablePhases parent_phases; ResettablePhases parent_phases;

2
target/cris/cpu.h
View file

@ -174,9 +174,7 @@ typedef struct CPUArchState {
* A CRIS CPU. * A CRIS CPU.
*/ */
struct ArchCPU { struct ArchCPU {
/*< private >*/
CPUState parent_obj; CPUState parent_obj;
/*< public >*/
CPUCRISState env; CPUCRISState env;
}; };

5
target/hexagon/cpu.h
View file

@ -130,17 +130,14 @@ typedef struct CPUArchState {
OBJECT_DECLARE_CPU_TYPE(HexagonCPU, HexagonCPUClass, HEXAGON_CPU) OBJECT_DECLARE_CPU_TYPE(HexagonCPU, HexagonCPUClass, HEXAGON_CPU)
typedef struct HexagonCPUClass { typedef struct HexagonCPUClass {
/*< private >*/
CPUClass parent_class; CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize; DeviceRealize parent_realize;
ResettablePhases parent_phases; ResettablePhases parent_phases;
} HexagonCPUClass; } HexagonCPUClass;
struct ArchCPU { struct ArchCPU {
/*< private >*/
CPUState parent_obj; CPUState parent_obj;
/*< public >*/
CPUHexagonState env; CPUHexagonState env;

2
target/hppa/cpu-qom.h
View file

@ -36,9 +36,7 @@ OBJECT_DECLARE_CPU_TYPE(HPPACPU, HPPACPUClass, HPPA_CPU)
* An HPPA CPU model. * An HPPA CPU model.
*/ */
struct HPPACPUClass { struct HPPACPUClass {
/*< private >*/
CPUClass parent_class; CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize; DeviceRealize parent_realize;
DeviceReset parent_reset; DeviceReset parent_reset;

2
target/hppa/cpu.h
View file

@ -247,9 +247,7 @@ typedef struct CPUArchState {
* An HPPA CPU. * An HPPA CPU.
*/ */
struct ArchCPU { struct ArchCPU {
/*< private >*/
CPUState parent_obj; CPUState parent_obj;
/*< public >*/
CPUHPPAState env; CPUHPPAState env;
QEMUTimer *alarm_timer; QEMUTimer *alarm_timer;

2
target/i386/cpu-qom.h
View file

@ -47,9 +47,7 @@ typedef struct X86CPUModel X86CPUModel;
* An x86 CPU model or family. * An x86 CPU model or family.
*/ */
struct X86CPUClass { struct X86CPUClass {
/*< private >*/
CPUClass parent_class; CPUClass parent_class;
/*< public >*/
/* CPU definition, automatically loaded by instance_init if not NULL. /* CPU definition, automatically loaded by instance_init if not NULL.
* Should be eventually replaced by subclass-specific property defaults. * Should be eventually replaced by subclass-specific property defaults.

2
target/i386/cpu.h
View file

@ -1897,9 +1897,7 @@ struct kvm_msrs;
* An x86 CPU. * An x86 CPU.
*/ */
struct ArchCPU { struct ArchCPU {
/*< private >*/
CPUState parent_obj; CPUState parent_obj;
/*< public >*/
CPUX86State env; CPUX86State env;
VMChangeStateEntry *vmsentry; VMChangeStateEntry *vmsentry;

4
target/loongarch/cpu.h
View file

@ -371,9 +371,7 @@ typedef struct CPUArchState {
* A LoongArch CPU. * A LoongArch CPU.
*/ */
struct ArchCPU { struct ArchCPU {
/*< private >*/
CPUState parent_obj; CPUState parent_obj;
/*< public >*/
CPULoongArchState env; CPULoongArchState env;
QEMUTimer timer; QEMUTimer timer;
@ -398,9 +396,7 @@ OBJECT_DECLARE_CPU_TYPE(LoongArchCPU, LoongArchCPUClass,
* A LoongArch CPU model. * A LoongArch CPU model.
*/ */
struct LoongArchCPUClass { struct LoongArchCPUClass {
/*< private >*/
CPUClass parent_class; CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize; DeviceRealize parent_realize;
ResettablePhases parent_phases; ResettablePhases parent_phases;

2
target/m68k/cpu-qom.h
View file

@ -35,9 +35,7 @@ OBJECT_DECLARE_CPU_TYPE(M68kCPU, M68kCPUClass, M68K_CPU)
* A Motorola 68k CPU model. * A Motorola 68k CPU model.
*/ */
struct M68kCPUClass { struct M68kCPUClass {
/*< private >*/
CPUClass parent_class; CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize; DeviceRealize parent_realize;
ResettablePhases parent_phases; ResettablePhases parent_phases;

2
target/m68k/cpu.h
View file

@ -164,9 +164,7 @@ typedef struct CPUArchState {
* A Motorola 68k CPU. * A Motorola 68k CPU.
*/ */
struct ArchCPU { struct ArchCPU {
/*< private >*/
CPUState parent_obj; CPUState parent_obj;
/*< public >*/
CPUM68KState env; CPUM68KState env;
}; };

2
target/microblaze/cpu-qom.h
View file

@ -35,9 +35,7 @@ OBJECT_DECLARE_CPU_TYPE(MicroBlazeCPU, MicroBlazeCPUClass, MICROBLAZE_CPU)
* A MicroBlaze CPU model. * A MicroBlaze CPU model.
*/ */
struct MicroBlazeCPUClass { struct MicroBlazeCPUClass {
/*< private >*/
CPUClass parent_class; CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize; DeviceRealize parent_realize;
ResettablePhases parent_phases; ResettablePhases parent_phases;

2
target/microblaze/cpu.h
View file

@ -343,9 +343,7 @@ typedef struct {
* A MicroBlaze CPU. * A MicroBlaze CPU.
*/ */
struct ArchCPU { struct ArchCPU {
/*< private >*/
CPUState parent_obj; CPUState parent_obj;
/*< public >*/
CPUMBState env; CPUMBState env;

2
target/mips/cpu-qom.h
View file

@ -39,9 +39,7 @@ OBJECT_DECLARE_CPU_TYPE(MIPSCPU, MIPSCPUClass, MIPS_CPU)
* A MIPS CPU model. * A MIPS CPU model.
*/ */
struct MIPSCPUClass { struct MIPSCPUClass {
/*< private >*/
CPUClass parent_class; CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize; DeviceRealize parent_realize;
ResettablePhases parent_phases; ResettablePhases parent_phases;

2
target/mips/cpu.h
View file

@ -1209,9 +1209,7 @@ typedef struct CPUArchState {
* A MIPS CPU. * A MIPS CPU.
*/ */
struct ArchCPU { struct ArchCPU {
/*< private >*/
CPUState parent_obj; CPUState parent_obj;
/*< public >*/
CPUMIPSState env; CPUMIPSState env;

4
target/nios2/cpu.h
View file

@ -42,9 +42,7 @@ OBJECT_DECLARE_CPU_TYPE(Nios2CPU, Nios2CPUClass, NIOS2_CPU)
* A Nios2 CPU model. * A Nios2 CPU model.
*/ */
struct Nios2CPUClass { struct Nios2CPUClass {
/*< private >*/
CPUClass parent_class; CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize; DeviceRealize parent_realize;
ResettablePhases parent_phases; ResettablePhases parent_phases;
@ -214,9 +212,7 @@ typedef struct {
* A Nios2 CPU. * A Nios2 CPU.
*/ */
struct ArchCPU { struct ArchCPU {
/*< private >*/
CPUState parent_obj; CPUState parent_obj;
/*< public >*/
CPUNios2State env; CPUNios2State env;

4
target/openrisc/cpu.h
View file

@ -39,9 +39,7 @@ OBJECT_DECLARE_CPU_TYPE(OpenRISCCPU, OpenRISCCPUClass, OPENRISC_CPU)
* A OpenRISC CPU model. * A OpenRISC CPU model.
*/ */
struct OpenRISCCPUClass { struct OpenRISCCPUClass {
/*< private >*/
CPUClass parent_class; CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize; DeviceRealize parent_realize;
ResettablePhases parent_phases; ResettablePhases parent_phases;
@ -301,9 +299,7 @@ typedef struct CPUArchState {
* A OpenRISC CPU. * A OpenRISC CPU.
*/ */
struct ArchCPU { struct ArchCPU {
/*< private >*/
CPUState parent_obj; CPUState parent_obj;
/*< public >*/
CPUOpenRISCState env; CPUOpenRISCState env;
}; };

2
target/ppc/cpu.h
View file

@ -1313,9 +1313,7 @@ typedef struct PPCVirtualHypervisorClass PPCVirtualHypervisorClass;
* A PowerPC CPU. * A PowerPC CPU.
*/ */
struct ArchCPU { struct ArchCPU {
/*< private >*/
CPUState parent_obj; CPUState parent_obj;
/*< public >*/
CPUPPCState env; CPUPPCState env;

3
target/riscv/cpu-qom.h
View file

@ -63,9 +63,8 @@ OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
* A RISCV CPU model. * A RISCV CPU model.
*/ */
struct RISCVCPUClass { struct RISCVCPUClass {
/*< private >*/
CPUClass parent_class; CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize; DeviceRealize parent_realize;
ResettablePhases parent_phases; ResettablePhases parent_phases;
}; };

2
target/riscv/cpu.h
View file

@ -411,9 +411,7 @@ struct CPUArchState {
* A RISCV CPU. * A RISCV CPU.
*/ */
struct ArchCPU { struct ArchCPU {
/* < private > */
CPUState parent_obj; CPUState parent_obj;
/* < public > */
CPURISCVState env; CPURISCVState env;

2
target/rx/cpu-qom.h
View file

@ -36,9 +36,7 @@ OBJECT_DECLARE_CPU_TYPE(RXCPU, RXCPUClass, RX_CPU)
* A RX CPU model. * A RX CPU model.
*/ */
struct RXCPUClass { struct RXCPUClass {
/*< private >*/
CPUClass parent_class; CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize; DeviceRealize parent_realize;
ResettablePhases parent_phases; ResettablePhases parent_phases;

2
target/rx/cpu.h
View file

@ -107,9 +107,7 @@ typedef struct CPUArchState {
* A RX CPU * A RX CPU
*/ */
struct ArchCPU { struct ArchCPU {
/*< private >*/
CPUState parent_obj; CPUState parent_obj;
/*< public >*/
CPURXState env; CPURXState env;
}; };

3
target/s390x/cpu-qom.h
View file

@ -49,9 +49,8 @@ typedef enum cpu_reset_type {
* An S/390 CPU model. * An S/390 CPU model.
*/ */
struct S390CPUClass { struct S390CPUClass {
/*< private >*/
CPUClass parent_class; CPUClass parent_class;
/*< public >*/
const S390CPUDef *cpu_def; const S390CPUDef *cpu_def;
bool kvm_required; bool kvm_required;
bool is_static; bool is_static;

2
target/s390x/cpu.h
View file

@ -172,9 +172,7 @@ static inline uint64_t *get_freg(CPUS390XState *cs, int nr)
* An S/390 CPU. * An S/390 CPU.
*/ */
struct ArchCPU { struct ArchCPU {
/*< private >*/
CPUState parent_obj; CPUState parent_obj;
/*< public >*/
CPUS390XState env; CPUS390XState env;
S390CPUModel *model; S390CPUModel *model;

2
target/sh4/cpu-qom.h
View file

@ -42,9 +42,7 @@ OBJECT_DECLARE_CPU_TYPE(SuperHCPU, SuperHCPUClass, SUPERH_CPU)
* A SuperH CPU model. * A SuperH CPU model.
*/ */
struct SuperHCPUClass { struct SuperHCPUClass {
/*< private >*/
CPUClass parent_class; CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize; DeviceRealize parent_realize;
ResettablePhases parent_phases; ResettablePhases parent_phases;

2
target/sh4/cpu.h
View file

@ -204,9 +204,7 @@ typedef struct CPUArchState {
* A SuperH CPU. * A SuperH CPU.
*/ */
struct ArchCPU { struct ArchCPU {
/*< private >*/
CPUState parent_obj; CPUState parent_obj;
/*< public >*/
CPUSH4State env; CPUSH4State env;
}; };

2
target/sparc/cpu-qom.h
View file

@ -40,9 +40,7 @@ typedef struct sparc_def_t sparc_def_t;
* A SPARC CPU model. * A SPARC CPU model.
*/ */
struct SPARCCPUClass { struct SPARCCPUClass {
/*< private >*/
CPUClass parent_class; CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize; DeviceRealize parent_realize;
ResettablePhases parent_phases; ResettablePhases parent_phases;

2
target/sparc/cpu.h
View file

@ -562,9 +562,7 @@ struct CPUArchState {
* A SPARC CPU. * A SPARC CPU.
*/ */
struct ArchCPU { struct ArchCPU {
/*< private >*/
CPUState parent_obj; CPUState parent_obj;
/*< public >*/
CPUSPARCState env; CPUSPARCState env;
}; };

2
target/tricore/cpu-qom.h
View file

@ -27,9 +27,7 @@
OBJECT_DECLARE_CPU_TYPE(TriCoreCPU, TriCoreCPUClass, TRICORE_CPU) OBJECT_DECLARE_CPU_TYPE(TriCoreCPU, TriCoreCPUClass, TRICORE_CPU)
struct TriCoreCPUClass { struct TriCoreCPUClass {
/*< private >*/
CPUClass parent_class; CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize; DeviceRealize parent_realize;
ResettablePhases parent_phases; ResettablePhases parent_phases;

2
target/tricore/cpu.h
View file

@ -63,9 +63,7 @@ typedef struct CPUArchState {
* A TriCore CPU. * A TriCore CPU.
*/ */
struct ArchCPU { struct ArchCPU {
/*< private >*/
CPUState parent_obj; CPUState parent_obj;
/*< public >*/
CPUTriCoreState env; CPUTriCoreState env;
}; };

2
target/xtensa/cpu-qom.h
View file

@ -47,9 +47,7 @@ typedef struct XtensaConfig XtensaConfig;
* An Xtensa CPU model. * An Xtensa CPU model.
*/ */
struct XtensaCPUClass { struct XtensaCPUClass {
/*< private >*/
CPUClass parent_class; CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize; DeviceRealize parent_realize;
ResettablePhases parent_phases; ResettablePhases parent_phases;

2
target/xtensa/cpu.h
View file

@ -556,9 +556,7 @@ struct CPUArchState {
* An Xtensa CPU. * An Xtensa CPU.
*/ */
struct ArchCPU { struct ArchCPU {
/*< private >*/
CPUState parent_obj; CPUState parent_obj;
/*< public >*/
CPUXtensaState env; CPUXtensaState env;
Clock *clock; Clock *clock;