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target/mips: Split out mips_env_mmu_index

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Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2024-01-28 16:00:39 +10:00
parent 4e999bf419
commit 6ebf33c5dc
6 changed files with 15 additions and 10 deletions
Download patch file Download diff file Expand all files Collapse all files

7
target/mips/cpu.h
View file

@ -1255,11 +1255,16 @@ static inline int hflags_mmu_index(uint32_t hflags)
} }
} }
static inline int cpu_mmu_index(CPUMIPSState *env, bool ifetch) static inline int mips_env_mmu_index(CPUMIPSState *env)
{ {
return hflags_mmu_index(env->hflags); return hflags_mmu_index(env->hflags);
} }
static inline int cpu_mmu_index(CPUMIPSState *env, bool ifetch)
{
return mips_env_mmu_index(env);
}
#include "exec/cpu-all.h" #include "exec/cpu-all.h"
/* Exceptions */ /* Exceptions */

2
target/mips/sysemu/physaddr.c
View file

@ -236,7 +236,7 @@ hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
int prot; int prot;
if (get_physical_address(env, &phys_addr, &prot, addr, MMU_DATA_LOAD, if (get_physical_address(env, &phys_addr, &prot, addr, MMU_DATA_LOAD,
cpu_mmu_index(env, false)) != 0) { mips_env_mmu_index(env)) != 0) {
return -1; return -1;
} }
return phys_addr; return phys_addr;

10
target/mips/tcg/msa_helper.c
View file

@ -8214,7 +8214,7 @@ void helper_msa_ffint_u_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
#if !defined(CONFIG_USER_ONLY) #if !defined(CONFIG_USER_ONLY)
#define MEMOP_IDX(DF) \ #define MEMOP_IDX(DF) \
MemOpIdx oi = make_memop_idx(MO_TE | DF | MO_UNALN, \ MemOpIdx oi = make_memop_idx(MO_TE | DF | MO_UNALN, \
cpu_mmu_index(env, false)); mips_env_mmu_index(env));
#else #else
#define MEMOP_IDX(DF) #define MEMOP_IDX(DF)
#endif #endif
@ -8323,7 +8323,7 @@ void helper_msa_st_b(CPUMIPSState *env, uint32_t wd,
target_ulong addr) target_ulong addr)
{ {
wr_t *pwd = &(env->active_fpu.fpr[wd].wr); wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
int mmu_idx = cpu_mmu_index(env, false); int mmu_idx = mips_env_mmu_index(env);
uintptr_t ra = GETPC(); uintptr_t ra = GETPC();
ensure_writable_pages(env, addr, mmu_idx, ra); ensure_writable_pages(env, addr, mmu_idx, ra);
@ -8337,7 +8337,7 @@ void helper_msa_st_h(CPUMIPSState *env, uint32_t wd,
target_ulong addr) target_ulong addr)
{ {
wr_t *pwd = &(env->active_fpu.fpr[wd].wr); wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
int mmu_idx = cpu_mmu_index(env, false); int mmu_idx = mips_env_mmu_index(env);
uintptr_t ra = GETPC(); uintptr_t ra = GETPC();
uint64_t d0, d1; uint64_t d0, d1;
@ -8358,7 +8358,7 @@ void helper_msa_st_w(CPUMIPSState *env, uint32_t wd,
target_ulong addr) target_ulong addr)
{ {
wr_t *pwd = &(env->active_fpu.fpr[wd].wr); wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
int mmu_idx = cpu_mmu_index(env, false); int mmu_idx = mips_env_mmu_index(env);
uintptr_t ra = GETPC(); uintptr_t ra = GETPC();
uint64_t d0, d1; uint64_t d0, d1;
@ -8379,7 +8379,7 @@ void helper_msa_st_d(CPUMIPSState *env, uint32_t wd,
target_ulong addr) target_ulong addr)
{ {
wr_t *pwd = &(env->active_fpu.fpr[wd].wr); wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
int mmu_idx = cpu_mmu_index(env, false); int mmu_idx = mips_env_mmu_index(env);
uintptr_t ra = GETPC(); uintptr_t ra = GETPC();
ensure_writable_pages(env, addr, mmu_idx, GETPC()); ensure_writable_pages(env, addr, mmu_idx, GETPC());

2
target/mips/tcg/sysemu/cp0_helper.c
View file

@ -1202,7 +1202,7 @@ void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
old, old & env->CP0_Cause & CP0Ca_IP_mask, old, old & env->CP0_Cause & CP0Ca_IP_mask,
val, val & env->CP0_Cause & CP0Ca_IP_mask, val, val & env->CP0_Cause & CP0Ca_IP_mask,
env->CP0_Cause); env->CP0_Cause);
switch (cpu_mmu_index(env, false)) { switch (mips_env_mmu_index(env)) {
case 3: case 3:
qemu_log(", ERL\n"); qemu_log(", ERL\n");
break; break;

2
target/mips/tcg/sysemu/special_helper.c
View file

@ -68,7 +68,7 @@ static void debug_post_eret(CPUMIPSState *env)
if (env->hflags & MIPS_HFLAG_DM) { if (env->hflags & MIPS_HFLAG_DM) {
qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC); qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
} }
switch (cpu_mmu_index(env, false)) { switch (mips_env_mmu_index(env)) {
case 3: case 3:
qemu_log(", ERL\n"); qemu_log(", ERL\n");
break; break;

2
target/mips/tcg/sysemu/tlb_helper.c
View file

@ -973,7 +973,7 @@ hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address,
/* data access */ /* data access */
ret = get_physical_address(env, &physical, &prot, address, access_type, ret = get_physical_address(env, &physical, &prot, address, access_type,
cpu_mmu_index(env, false)); mips_env_mmu_index(env));
if (ret == TLBRET_MATCH) { if (ret == TLBRET_MATCH) {
return physical; return physical;
} }