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Replace is_user variable with mmu_idx in softmmu core,

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allowing support of more than 2 mmu access modes.
Add backward compatibility is_user variable in targets code when needed.
Implement per target cpu_mmu_index function, avoiding duplicated code
  and #ifdef TARGET_xxx in softmmu core functions.
Implement per target mmu modes definitions. As an example, add PowerPC
  hypervisor mode definition and Alpha executive and kernel modes definitions.
Optimize PowerPC case, precomputing mmu_idx when MSR register changes
  and using the same definition in code translation code.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3384 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
j_mayer 2007-10-14 07:07:08 +00:00
parent d0f48074db
commit 6ebbf39000
48 changed files with 362 additions and 275 deletions
Download patch file Download diff file Expand all files Collapse all files

11
target-mips/cpu.h
View file

@ -107,6 +107,8 @@ struct CPUMIPSFPUContext {
#define FP_UNIMPLEMENTED 32
};
#define NB_MMU_MODES 2
typedef struct CPUMIPSMVPContext CPUMIPSMVPContext;
struct CPUMIPSMVPContext {
int32_t CP0_MVPControl;
@ -484,6 +486,15 @@ int cpu_mips_register (CPUMIPSState *env, mips_def_t *def);
#define cpu_signal_handler cpu_mips_signal_handler
#define cpu_list mips_cpu_list
/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _kernel
#define MMU_MODE1_SUFFIX _user
#define MMU_USER_IDX 1
static inline int cpu_mmu_index (CPUState *env)
{
return (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM ? 1 : 0;
}
#include "cpu-all.h"
/* Memory access type :

2
target-mips/exec.h
View file

@ -105,7 +105,7 @@ void do_pmon (int function);
void dump_sc (void);
int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
int is_user, int is_softmmu);
int mmu_idx, int is_softmmu);
void do_interrupt (CPUState *env);
void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra);

8
target-mips/helper.c
View file

@ -229,7 +229,7 @@ void cpu_mips_init_mmu (CPUState *env)
#endif /* !defined(CONFIG_USER_ONLY) */
int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
int is_user, int is_softmmu)
int mmu_idx, int is_softmmu)
{
target_ulong physical;
int prot;
@ -241,8 +241,8 @@ int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
#if 0
cpu_dump_state(env, logfile, fprintf, 0);
#endif
fprintf(logfile, "%s pc " TARGET_FMT_lx " ad " TARGET_FMT_lx " rw %d is_user %d smmu %d\n",
__func__, env->PC[env->current_tc], address, rw, is_user, is_softmmu);
fprintf(logfile, "%s pc " TARGET_FMT_lx " ad " TARGET_FMT_lx " rw %d mmu_idx %d smmu %d\n",
__func__, env->PC[env->current_tc], address, rw, mmu_idx, is_softmmu);
}
rw &= 1;
@ -265,7 +265,7 @@ int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
if (ret == TLBRET_MATCH) {
ret = tlb_set_page(env, address & TARGET_PAGE_MASK,
physical & TARGET_PAGE_MASK, prot,
is_user, is_softmmu);
mmu_idx, is_softmmu);
} else if (ret < 0) {
do_fault:
switch (ret) {

4
target-mips/op_helper.c
View file

@ -563,7 +563,7 @@ static void do_unaligned_access (target_ulong addr, int is_write, int is_user, v
do_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL);
}
void tlb_fill (target_ulong addr, int is_write, int is_user, void *retaddr)
void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
{
TranslationBlock *tb;
CPUState *saved_env;
@ -574,7 +574,7 @@ void tlb_fill (target_ulong addr, int is_write, int is_user, void *retaddr)
generated code */
saved_env = env;
env = cpu_single_env;
ret = cpu_mips_handle_mmu_fault(env, addr, is_write, is_user, 1);
ret = cpu_mips_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
if (ret) {
if (retaddr) {
/* now we have a real cpu fault */