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hw/riscv: sifive_u: Add a dummy L2 cache controller device

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It is enough to simply map the SiFive FU540 L2 cache controller
into the MMIO space using create_unimplemented_device(), with an
FDT fragment generated, to make the latest upstream U-Boot happy.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1595227748-24720-1-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Bin Meng 2020-07-19 23:49:08 -07:00 • committed by Alistair Francis
parent ec80f87459
commit 6eaf9cf56f
2 changed files with 26 additions and 0 deletions
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4
include/hw/riscv/sifive_u.h
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@ -71,6 +71,7 @@ enum {
SIFIVE_U_DEBUG,
SIFIVE_U_MROM,
SIFIVE_U_CLINT,
SIFIVE_U_L2CC,
SIFIVE_U_L2LIM,
SIFIVE_U_PLIC,
SIFIVE_U_PRCI,
@ -86,6 +87,9 @@ enum {
};
enum {
SIFIVE_U_L2CC_IRQ0 = 1,
SIFIVE_U_L2CC_IRQ1 = 2,
SIFIVE_U_L2CC_IRQ2 = 3,
SIFIVE_U_UART0_IRQ = 4,
SIFIVE_U_UART1_IRQ = 5,
SIFIVE_U_GPIO_IRQ0 = 7,