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https://github.com/Motorhead1991/qemu.git
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rust/timer/hpet: add qom and qdev APIs support
Implement QOM & QAPI support for HPET device. Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Link: https://lore.kernel.org/r/20250210030051.2562726-10-zhao1.liu@intel.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Zhao Liu
Paolo Bonzini
parent
269a8f155c
commit
6e90a8f813
3 changed files with 273 additions and 11 deletions
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@ -2,8 +2,6 @@
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// Author(s): Zhao Liu <zhai1.liu@intel.com>
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// SPDX-License-Identifier: GPL-2.0-or-later
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#![allow(dead_code)]
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use std::ptr::addr_of_mut;
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use qemu_api::{cell::bql_locked, impl_zeroable, zeroable::Zeroable};
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@ -2,21 +2,33 @@
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// Author(s): Zhao Liu <zhai1.liu@intel.com>
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// SPDX-License-Identifier: GPL-2.0-or-later
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#![allow(dead_code)]
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use std::ptr::{addr_of_mut, null_mut, NonNull};
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use std::{
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ffi::CStr,
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ptr::{addr_of_mut, null_mut, NonNull},
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slice::from_ref,
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};
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use qemu_api::{
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bindings::{address_space_memory, address_space_stl_le},
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bindings::{
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address_space_memory, address_space_stl_le, qdev_prop_bit, qdev_prop_bool,
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qdev_prop_uint32, qdev_prop_uint8,
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},
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c_str,
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cell::{BqlCell, BqlRefCell},
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irq::InterruptSource,
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memory::{MemoryRegion, MEMTXATTRS_UNSPECIFIED},
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memory::{
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hwaddr, MemoryRegion, MemoryRegionOps, MemoryRegionOpsBuilder, MEMTXATTRS_UNSPECIFIED,
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},
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prelude::*,
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qom::ParentField,
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qdev::{DeviceImpl, DeviceMethods, DeviceState, Property, ResetType, ResettablePhasesImpl},
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qom::{ObjectImpl, ObjectType, ParentField},
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qom_isa,
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sysbus::SysBusDevice,
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timer::{Timer, CLOCK_VIRTUAL},
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};
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use crate::fw_cfg::HPETFwConfig;
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/// Register space for each timer block (`HPET_BASE` is defined in hpet.h).
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const HPET_REG_SPACE_LEN: u64 = 0x400; // 1024 bytes
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@ -139,8 +151,7 @@ fn timer_handler(timer_cell: &BqlRefCell<HPETTimer>) {
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/// HPET Timer Abstraction
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#[repr(C)]
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#[derive(Debug, Default)]
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#[cfg_attr(has_offset_of, derive(qemu_api_macros::offsets))]
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#[derive(Debug, Default, qemu_api_macros::offsets)]
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pub struct HPETTimer {
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/// timer N index within the timer block (`HPETState`)
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#[doc(alias = "tn")]
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@ -451,11 +462,41 @@ impl HPETTimer {
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}
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self.update_irq(true);
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}
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const fn read(&self, addr: hwaddr, _size: u32) -> u64 {
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let shift: u64 = (addr & 4) * 8;
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match addr & !4 {
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HPET_TN_CFG_REG => self.config >> shift, // including interrupt capabilities
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HPET_TN_CMP_REG => self.cmp >> shift, // comparator register
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HPET_TN_FSB_ROUTE_REG => self.fsb >> shift,
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_ => {
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// TODO: Add trace point - trace_hpet_ram_read_invalid()
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// Reserved.
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0
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}
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}
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}
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fn write(&mut self, addr: hwaddr, value: u64, size: u32) {
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let shift = ((addr & 4) * 8) as u32;
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let len = std::cmp::min(size * 8, 64 - shift);
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match addr & !4 {
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HPET_TN_CFG_REG => self.set_tn_cfg_reg(shift, len, value),
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HPET_TN_CMP_REG => self.set_tn_cmp_reg(shift, len, value),
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HPET_TN_FSB_ROUTE_REG => self.set_tn_fsb_route_reg(shift, len, value),
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_ => {
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// TODO: Add trace point - trace_hpet_ram_write_invalid()
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// Reserved.
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}
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}
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}
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}
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/// HPET Event Timer Block Abstraction
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#[repr(C)]
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#[derive(qemu_api_macros::offsets)]
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#[derive(qemu_api_macros::Object, qemu_api_macros::offsets)]
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pub struct HPETState {
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parent_obj: ParentField<SysBusDevice>,
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iomem: MemoryRegion,
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@ -626,4 +667,223 @@ impl HPETState {
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self.counter
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.set(self.counter.get().deposit(shift, len, val));
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}
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unsafe fn init(&mut self) {
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static HPET_RAM_OPS: MemoryRegionOps<HPETState> =
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MemoryRegionOpsBuilder::<HPETState>::new()
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.read(&HPETState::read)
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.write(&HPETState::write)
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.native_endian()
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.valid_sizes(4, 8)
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.impl_sizes(4, 8)
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.build();
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// SAFETY:
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// self and self.iomem are guaranteed to be valid at this point since callers
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// must make sure the `self` reference is valid.
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MemoryRegion::init_io(
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unsafe { &mut *addr_of_mut!(self.iomem) },
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addr_of_mut!(*self),
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&HPET_RAM_OPS,
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"hpet",
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HPET_REG_SPACE_LEN,
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);
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}
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fn post_init(&self) {
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self.init_mmio(&self.iomem);
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for irq in self.irqs.iter() {
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self.init_irq(irq);
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}
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}
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fn realize(&self) {
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if self.int_route_cap == 0 {
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// TODO: Add error binding: warn_report()
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println!("Hpet's hpet-intcap property not initialized");
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}
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self.hpet_id.set(HPETFwConfig::assign_hpet_id());
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if self.num_timers.get() < HPET_MIN_TIMERS {
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self.num_timers.set(HPET_MIN_TIMERS);
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} else if self.num_timers.get() > HPET_MAX_TIMERS {
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self.num_timers.set(HPET_MAX_TIMERS);
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}
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self.init_timer();
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// 64-bit General Capabilities and ID Register; LegacyReplacementRoute.
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self.capability.set(
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HPET_CAP_REV_ID_VALUE << HPET_CAP_REV_ID_SHIFT |
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1 << HPET_CAP_COUNT_SIZE_CAP_SHIFT |
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1 << HPET_CAP_LEG_RT_CAP_SHIFT |
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HPET_CAP_VENDER_ID_VALUE << HPET_CAP_VENDER_ID_SHIFT |
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((self.num_timers.get() - 1) as u64) << HPET_CAP_NUM_TIM_SHIFT | // indicate the last timer
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(HPET_CLK_PERIOD * FS_PER_NS) << HPET_CAP_CNT_CLK_PERIOD_SHIFT, // 10 ns
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);
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self.init_gpio_in(2, HPETState::handle_legacy_irq);
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self.init_gpio_out(from_ref(&self.pit_enabled));
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}
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fn reset_hold(&self, _type: ResetType) {
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let sbd = self.upcast::<SysBusDevice>();
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for timer in self.timers.iter().take(self.num_timers.get()) {
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timer.borrow_mut().reset();
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}
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self.counter.set(0);
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self.config.set(0);
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self.pit_enabled.set(true);
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self.hpet_offset.set(0);
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HPETFwConfig::update_hpet_cfg(
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self.hpet_id.get(),
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self.capability.get() as u32,
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sbd.mmio[0].addr,
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);
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// to document that the RTC lowers its output on reset as well
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self.rtc_irq_level.set(0);
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}
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fn timer_and_addr(&self, addr: hwaddr) -> Option<(&BqlRefCell<HPETTimer>, hwaddr)> {
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let timer_id: usize = ((addr - 0x100) / 0x20) as usize;
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// TODO: Add trace point - trace_hpet_ram_[read|write]_timer_id(timer_id)
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if timer_id > self.num_timers.get() {
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// TODO: Add trace point - trace_hpet_timer_id_out_of_range(timer_id)
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None
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} else {
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// Keep the complete address so that HPETTimer's read and write could
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// detect the invalid access.
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Some((&self.timers[timer_id], addr & 0x1F))
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}
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}
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fn read(&self, addr: hwaddr, size: u32) -> u64 {
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let shift: u64 = (addr & 4) * 8;
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// address range of all TN regs
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// TODO: Add trace point - trace_hpet_ram_read(addr)
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if (0x100..=0x3ff).contains(&addr) {
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match self.timer_and_addr(addr) {
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None => 0, // Reserved,
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Some((timer, tn_addr)) => timer.borrow_mut().read(tn_addr, size),
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}
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} else {
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match addr & !4 {
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HPET_CAP_REG => self.capability.get() >> shift, /* including HPET_PERIOD 0x004 */
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// (CNT_CLK_PERIOD field)
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HPET_CFG_REG => self.config.get() >> shift,
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HPET_COUNTER_REG => {
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let cur_tick: u64 = if self.is_hpet_enabled() {
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self.get_ticks()
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} else {
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self.counter.get()
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};
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// TODO: Add trace point - trace_hpet_ram_read_reading_counter(addr & 4,
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// cur_tick)
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cur_tick >> shift
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}
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HPET_INT_STATUS_REG => self.int_status.get() >> shift,
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_ => {
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// TODO: Add trace point- trace_hpet_ram_read_invalid()
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// Reserved.
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0
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}
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}
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}
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}
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fn write(&self, addr: hwaddr, value: u64, size: u32) {
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let shift = ((addr & 4) * 8) as u32;
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let len = std::cmp::min(size * 8, 64 - shift);
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// TODO: Add trace point - trace_hpet_ram_write(addr, value)
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if (0x100..=0x3ff).contains(&addr) {
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match self.timer_and_addr(addr) {
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None => (), // Reserved.
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Some((timer, tn_addr)) => timer.borrow_mut().write(tn_addr, value, size),
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}
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} else {
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match addr & !0x4 {
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HPET_CAP_REG => {} // General Capabilities and ID Register: Read Only
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HPET_CFG_REG => self.set_cfg_reg(shift, len, value),
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HPET_INT_STATUS_REG => self.set_int_status_reg(shift, len, value),
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HPET_COUNTER_REG => self.set_counter_reg(shift, len, value),
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_ => {
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// TODO: Add trace point - trace_hpet_ram_write_invalid()
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// Reserved.
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}
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}
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}
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}
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}
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qom_isa!(HPETState: SysBusDevice, DeviceState, Object);
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unsafe impl ObjectType for HPETState {
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// No need for HPETClass. Just like OBJECT_DECLARE_SIMPLE_TYPE in C.
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type Class = <SysBusDevice as ObjectType>::Class;
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const TYPE_NAME: &'static CStr = crate::TYPE_HPET;
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}
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impl ObjectImpl for HPETState {
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type ParentType = SysBusDevice;
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const INSTANCE_INIT: Option<unsafe fn(&mut Self)> = Some(Self::init);
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const INSTANCE_POST_INIT: Option<fn(&Self)> = Some(Self::post_init);
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}
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// TODO: Make these properties user-configurable!
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qemu_api::declare_properties! {
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HPET_PROPERTIES,
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qemu_api::define_property!(
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c_str!("timers"),
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HPETState,
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num_timers,
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unsafe { &qdev_prop_uint8 },
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u8,
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default = HPET_MIN_TIMERS
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),
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qemu_api::define_property!(
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c_str!("msi"),
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HPETState,
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flags,
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unsafe { &qdev_prop_bit },
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u32,
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bit = HPET_FLAG_MSI_SUPPORT_SHIFT as u8,
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default = false,
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),
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qemu_api::define_property!(
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c_str!("hpet-intcap"),
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HPETState,
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int_route_cap,
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unsafe { &qdev_prop_uint32 },
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u32,
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default = 0
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),
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qemu_api::define_property!(
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c_str!("hpet-offset-saved"),
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HPETState,
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hpet_offset_saved,
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unsafe { &qdev_prop_bool },
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bool,
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default = true
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),
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}
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impl DeviceImpl for HPETState {
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fn properties() -> &'static [Property] {
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&HPET_PROPERTIES
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}
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const REALIZE: Option<fn(&Self)> = Some(Self::realize);
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}
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impl ResettablePhasesImpl for HPETState {
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const HOLD: Option<fn(&Self, ResetType)> = Some(Self::reset_hold);
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}
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@ -7,5 +7,9 @@
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//! This library implements a device model for the IA-PC HPET (High
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//! Precision Event Timers) device in QEMU.
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use qemu_api::c_str;
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pub mod fw_cfg;
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pub mod hpet;
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pub const TYPE_HPET: &::std::ffi::CStr = c_str!("hpet");
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