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target/arm: Convert MSR (reg), MRS, SYS, SYSL to decodetree

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Convert MSR (reg), MRS, SYS, SYSL to decodetree.  For QEMU these are
all essentially the same instruction (system register access).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230602155223.2040685-7-peter.maydell@linaro.org
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
This commit is contained in:
Peter Maydell 2023-06-19 11:20:20 +01:00
parent 45d063d163
commit 6e3c8049ad
2 changed files with 13 additions and 27 deletions
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8
target/arm/tcg/a64.decode
View file

@ -207,3 +207,11 @@ MSR_i_TCO 1101 0101 0000 0 011 0100 .... 100 11111 @msr_i
MSR_i_DAIFSET 1101 0101 0000 0 011 0100 .... 110 11111 @msr_i MSR_i_DAIFSET 1101 0101 0000 0 011 0100 .... 110 11111 @msr_i
MSR_i_DAIFCLEAR 1101 0101 0000 0 011 0100 .... 111 11111 @msr_i MSR_i_DAIFCLEAR 1101 0101 0000 0 011 0100 .... 111 11111 @msr_i
MSR_i_SVCR 1101 0101 0000 0 011 0100 0 mask:2 imm:1 011 11111 MSR_i_SVCR 1101 0101 0000 0 011 0100 0 mask:2 imm:1 011 11111
# MRS, MSR (register), SYS, SYSL. These are all essentially the
# same instruction as far as QEMU is concerned.
# NB: op0 is bits [20:19], but op0=0b00 is other insns, so we have
# to hand-decode it.
SYS 1101 0101 00 l:1 01 op1:3 crn:4 crm:4 op2:3 rt:5 op0=1
SYS 1101 0101 00 l:1 10 op1:3 crn:4 crm:4 op2:3 rt:5 op0=2
SYS 1101 0101 00 l:1 11 op1:3 crn:4 crm:4 op2:3 rt:5 op0=3

30
target/arm/tcg/translate-a64.c
View file

@ -2122,7 +2122,7 @@ static void gen_sysreg_undef(DisasContext *s, bool isread,
* These are all essentially the same insn in 'read' and 'write' * These are all essentially the same insn in 'read' and 'write'
* versions, with varying op0 fields. * versions, with varying op0 fields.
*/ */
static void handle_sys(DisasContext *s, uint32_t insn, bool isread, static void handle_sys(DisasContext *s, bool isread,
unsigned int op0, unsigned int op1, unsigned int op2, unsigned int op0, unsigned int op1, unsigned int op2,
unsigned int crn, unsigned int crm, unsigned int rt) unsigned int crn, unsigned int crm, unsigned int rt)
{ {
@ -2307,28 +2307,10 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
} }
} }
/* System static bool trans_SYS(DisasContext *s, arg_SYS *a)
* 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
* +---------------------+---+-----+-----+-------+-------+-----+------+
* | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
* +---------------------+---+-----+-----+-------+-------+-----+------+
*/
static void disas_system(DisasContext *s, uint32_t insn)
{ {
unsigned int l, op0, op1, crn, crm, op2, rt; handle_sys(s, a->l, a->op0, a->op1, a->op2, a->crn, a->crm, a->rt);
l = extract32(insn, 21, 1); return true;
op0 = extract32(insn, 19, 2);
op1 = extract32(insn, 16, 3);
crn = extract32(insn, 12, 4);
crm = extract32(insn, 8, 4);
op2 = extract32(insn, 5, 3);
rt = extract32(insn, 0, 5);
if (op0 == 0) {
unallocated_encoding(s);
return;
}
handle_sys(s, insn, l, op0, op1, op2, crn, crm, rt);
} }
/* Exception generation /* Exception generation
@ -2435,11 +2417,7 @@ static void disas_b_exc_sys(DisasContext *s, uint32_t insn)
switch (extract32(insn, 25, 7)) { switch (extract32(insn, 25, 7)) {
case 0x6a: /* Exception generation / System */ case 0x6a: /* Exception generation / System */
if (insn & (1 << 24)) { if (insn & (1 << 24)) {
if (extract32(insn, 22, 2) == 0) {
disas_system(s, insn);
} else {
unallocated_encoding(s); unallocated_encoding(s);
}
} else { } else {
disas_exc(s, insn); disas_exc(s, insn);
} }